High speed latch circuit

An integrated circuit comprising:

• a plurality of latch circuits, one or more of the latch circuits each comprising:
• at least one set of cross-coupled transistor devices arranged between an upper supply terminal of the circuit and a lower supply terminal of the circuit;
• a first input transistor device coupled in parallel with a first one of the transistor devices of the set of cross-coupled transistor devices;
• and
• a second input transistor device coupled in parallel with a second one of the transistor devices of the set of cross-coupled transistor devices;
• the first and second input transistor devices being adapted for application of respective uncomplemented and complemented inputs thereto during an initialization mode of the latch circuit;
• at least one output signal being generatable at a corresponding at least one output terminal associated with the at least one set of cross-coupled transistor devices during an evaluation mode of the latch circuit;
• wherein the at least one set of cross-coupled transistor devices comprises an upper set of cross-coupled transistor devices and a lower set of cross-coupled transistor devices, the upper and lower sets being arranged in series between the upper and lower supply terminals, the first and second input transistor devices being coupled in parallel with corresponding first and second transistor devices of the lower set of cross-coupled transistor devices, the latch circuit further including third and fourth input transistor devices coupled in parallel with corresponding first and second transistor devices of the upper set of cross-coupled transistor devices, the first and third input transistor devices each being adapted to receive the uncomplemented input, the second and fourth input transistor devices each being adapted to receive the complemented input.

A method for use in a latch circuit, the latch circuit comprising at least one set of cross-coupled transistor devices arranged between an upper supply terminal of the circuit and a lower supply terminal of the circuit, a first input transistor device coupled in parallel with a first one of the transistor devices of the set of cross-coupled transistor devices, and a second input transistor device coupled in parallel with a second one of the transistor devices of the set of cross-coupled transistor devices, wherein the at least one set of cross-coupled transistor devices comprises an upper set of cross-coupled transistor devices and a lower set of cross-coupled transistor devices, the upper and lower sets being arranged in series between the upper and lower supply terminals, the first and second input transistor devices being coupled in parallel with corresponding first and second transistor devices of the lower set of cross-coupled transistor devices, the latch circuit further including third and fourth input transistor devices coupled in parallel with corresponding first and second transistor devices of the upper set of cross-coupled transistor devices, the method comprising the steps of:

• applying to the first and second input transistor devices respective uncomplemented and complemented inputs, and applying to the third and fourth input transistor devices the respective uncomplemented and complemented inputs, during an initialization mode of the latch circuit;
• and
• generating at least one output signal at a corresponding at least one output terminal associated with the at least one set of cross-coupled transistor devices during an evaluation mode of the latch circuit.