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US 6,472,919 B1Granted
Low voltage latch with uniform stack height
AssigneeSun Microsystems, Inc.
InventorJames B. Burr
Life of this patent
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Abstract
Low voltage latches are designed such that all the transistors included in the latch are low threshold transistors and voltage scalability of the latches of the invention is further increased by designing latches with uniform stack height components. One embodiment of the invention allows for minimum supply voltages of 60 millivolts, an improvement of over thirteen hundred percent compared with the typical prior art minimum voltage requirement of 800 millivolts.
Claims8
A latch, said latch comprising:
- an input line;
- a first node coupled to said input line;
- a first pass gate coupled to said first node;
- a second node coupled to said first pass gate such that said first pass gate is coupled between said first node and said second node;
- a first inverter having an input coupled to said second node, said first inverter comprising transistors, said first inverter having an output;
- a feedback stage having an input node coupled to said output of said first inverter and an output node coupled to said second node, said feedback stage comprising:
- a first transistor comprising a first flow electrode, a second flow electrode and a control electrode, said first transistor control electrode being coupled to said feedback stage input node;
- a second transistor comprising a first flow electrode, a second flow electrode and a control electrode, said second transistor control electrode being coupled to said feedback stage input node and said first transistor control electrode, said second transistor first flow electrode being coupled to said second flow electrode of said first transistor;
- a third transistor comprising a first flow electrode, a second flow electrode and a control electrode, said third transistor second flow electrode being coupled to said first transistor second flow electrode and said second transistor first flow electrodes;
- a fourth transistor comprising a first flow electrode, a second flow electrode and a control electrode, said fourth transistor first flow electrode being couple to said first transistor second flow electrode said second transistor first flow, electrode and said third transistor second flow electrode
- a feedback pass gate coupled between said first transistor second flow electrode and said second transistor first flow electrode;
- wherein
- each of said transistors of said first inverter and said first, second, third and fourth transistors of said feedback stage has approximately the same channel length and approximately the same channel width as all other transistors of said first inverter and said first, second, third and fourth transistors of said feedback stage, further wherein;
- a stack height of said transistors of said feedback stage is equal to a stack height of said transistors of said feedback pass gate;
- further wherein;
- said transistors of said first inverter and said first, second, third and fourth transistors of said feedback stage are low threshold transistors.
13 more elements
A latch, said latch comprising:
- an input line;
- a first node coupled to said input line;
- a first pass gate coupled to said first node;
- a second node coupled to said first pass gate such that said first pass gate is coupled between said first node and said second node;
- a first inverter having an input coupled to said second node, said first inverter comprising transistors, said first inverter having an output;
- a feedback-stage having an input node coupled to said output of said first inverter and an output node coupled to said second node, said feedback stage comprising:
- a first transistor comprising a first flow electrode, a second flow electrode and a control electrode, said first transistor control electrode being coupled to said feedback stage input node;
- a second transistor comprising a first flow electrode, a second flow electrode and a control electrode, said second transistor control electrode being coupled to said feedback stage input node and said first transistor control electrode, said second transistor first flow electrode being coupled to said second flow electrode of said first transistor;
- a third transistor comprising a first flow electrode, a second flow electrode and a control electrode, said third transistor second flow electrode being coupled to said first transistor second flow electrode and said second transistor first flow electrode;
- a fourth transistor comprising a first flow electrode, a second flow electrode and a control electrode, said fourth transistor first flow electrode being coupled to said first transistor second flown electrode, said second transistor first flow electrode;
- and said third transistor second flow electrode;
- and said third transistor second flow electrode;
- a feedback pass gate coupled between said first transistor second flow electrode and said second transistor first flow electrode;
- wherein
- each of said transistors of said first inverter and said first, second, third and fourth transistors of said feedback stage has approximately the same channel length and approximately the same channel width as all other transistors of said first inverter and said first, second, third and fourth transistors of said feedback stage, further wherein;
- a stack height of said transistors of said feedback stage is equal to a stack height of said transistors of said feedback pass gate;
- further wherein;
- said transistors of said first inverter and said first, second, third and fourth transistors of said feedback stage are low threshold transistors having unbiased threshold voltages of less than 300 millivolts and a supply voltage supplied to said latch is less than said supply voltage of 300 millivolts.
15 more elements
A method of designing a latch, said method comprising:
- providing an input line;
- coupling a first node to said input line;
- coupling a first pass gate to said first node;
- coupling said first pass gate to a second node such that said first pass gate is coupled between said first node and said second node;
- providing a first inverter having an input, said first inverter comprising transistors, said first inverter having an output;
- coupling said first inverter input to said second node;
- providing a feedback stage having an input node and an output node, said feedback stage comprising:
- a first transistor comprising a first flow electrode, a second flow electrode and a control electrode, said first transistor control electrode being coupled to said feedback stage input node;
- a second transistor comprising a first flow electrode, a second flow electrode and a control electrode, said second transistor control electrode being coupled to said feedback stage input node and said first transistor control electrode;
- a third transistor comprising a first flow electrode, a second flow electrode and a control electrode;
- a fourth transistor comprising a first flow electrode, a second flow electrode and a control electrode;
- coupling said first transistor second flow electrode to said second transistor first flow electrode said third transistor second flow electrode and said fourth transistor first flow electrode;
- coupling said input node of said feedback stage to said output of said first inverter;
- coupling said output node of said feedback stage to said second node;
- and
- coupling a feedback pass gate between said first transistor second flow electrode and said second transistor first flow electrode, wherein;
- each of said transistors of said first inverter and said first, second, third and fourth transistors of said feedback stage has approximately the same channel length and approximately the same channel width as all other transistors of said first inverter and said first, second, third and fourth transistors of said feedback stage, further wherein;
- a stack height of said transistors of said feedback stage is equal to a stack height of said transistors of said feedback pass gate;
- further wherein;
- said transistors of said first inverter and said first, second, third and fourth transistors of said feedback stage are low threshold transistors.
17 more elements
A method of designing a latch, said method comprising:
- providing an input line;
- coupling a first node to said input line;
- coupling a first pass gate to said first node;
- coupling said first pass gate to a second node such that said first pass gate is coupled between said first node and said second node;
- providing a first inverter having an input, said first inverter comprising transistors, said first inverter having an output;
- coupling said first inverter input to said second node;
- providing a feedback stage having an input node and an output node, said feedback stage comprising:
- a first transistor comprising a first flow electrode, a second flow electrode and a control electrode, said first transistor control electrode being coupled to said feedback stage input node;
- a second transistor comprising a first flow electrode, a second flow electrode and a control electrode, said second transistor control electrode being coupled to said feedback stage input node and said first transistor control electrode;
- a third transistor comprising a first flow electrode, a second flow electrode and a control electrode;
- a fourth transistor comprising a first flow electrode, a second flow electrode and a control electrode;
- coupling said first transistor second flow electrode to said second transistor first flow electrode said third transistor second flow electrode and said fourth transistor first flow electrode;
- coupling said input node of said feedback stage to said output of said first inverter;
- coupling said output node of said feedback stage to said second node;
- coupling a feedback pass gate between said first transistor second flow electrode and said second transistor first flow electrode;
- and
- providing a supply voltage to said latch, said supply voltage being less than 300 millivolts;
- wherein
- each of said transistors of said first inverter and said first, second, third and fourth transistors of said feedback stage has approximately the same channel length and approximately the same channel width as all other transistors of said first inverter and said first, second, third and fourth transistors of said feedback stage, further wherein;
- a stack height of said transistors of said feedback stage is equal to a stack height of said transistors of said feedback pass gate;
- further wherein;
- said transistors of said first inverter and said first, second, third and fourth transistors of said feedback stage are low threshold transistors having unbiased threshold voltages of less than said supply voltage of 300 millivolts.
19 more elements
Dependencies are inferred from the claim text.