Self-referencing slicer method and apparatus for high-accuracy clock duty cycle generation
AssigneeLevel One Communications, Inc.
InventorsPaulius M. Mosinskis, Amit Gattani
Life of this patent
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Abstract
A system and method for regulating the duty cycle of a digital clock signal derived from an oscillator signal. The oscillator signal is DC-biased to a DC value representing an average DC value of an ideal digital clock signal having a 50% duty cycle. The DC-biased oscillator signal is compared to a reference voltage. The digital clock signal is generated as a substantially square wave signal having first and second logic levels, and is generated in response to the comparison of the DC-biased oscillator signal and the reference voltage. The DC component of the generated digital clock signal is then used as the reference voltage.
Claims19
An apparatus for regulating a duty cycle of a digital clock signal, comprising:
- an oscillator generating a substantially sinusoidal signal;
- a voltage divider circuit to generate an input signal from the substantially sinusoidal signal, wherein the input signal has a DC content of approximately one half of a supply voltage;
- a slicer comprising:
- a first input coupled to the voltage divider circuit to receive the input signal;
- a second input coupled to receive a reference voltage;
- and
- an output to supply the digital clock signal having a 50% duty cycle;
- and
- a passive feedback circuit coupled between the output of the slicer and the second input of the slicer, wherein only the DC content of the digital clock signal provides the reference voltage at the second input of the slicer.
A method for regulating a duty cycle of a digital clock signal, comprising:
- generating a substantially sinusoidal input signal having a DC content of approximately one half of a supply voltage;
- comparing a reference voltage with the input signal to generate an output digital signal having a 50% duty cycle;
- and
- automatically adjusting the reference voltage, using a passive low pass filter, in response to changes in the duty cycle of the output digital signal to maintain a 50% duty cycle for the output digital signal.
A circuit for regulating a duty cycle of a digital clock signal, comprising:
- an oscillator generating a substantially sinusoidal signal;
- a slicer for comparing a reference voltage with an input signal derived from the substantially sinusoidal signal having a DC content of approximately one half of a supply voltage to generate an output digital signal having a 50% duty cycle;
- and
- a passive component feedback circuit for automatically adjusting the reference voltage in response to changes in the duty cycle of the output digital signal to maintain a 50% duty cycle for the output digital signal.
Dependencies are inferred from the claim text.