Semiconductor integrated circuit device having compensation for wiring distance delays
AssigneeHitachi, Ltd.
InventorsTatsumi Yamauchi, Kazuharu Kuchimachi
Life of this patent
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Abstract
A third gate circuit which is controlled by a clock signal and operates upon the detection of change of a signal on a critical path driven by a first gate circuit and transmits a signal provided by the first gate circuit to a second gate circuit is connected to the critical path at a position near the second gate circuit. The third gate circuits operates upon the detection of change of the signal to increase the speed of change of the signal. Thus, the ratio of a delay time attributable to wiring resistance in the critical path of a semiconductor integrated circuit is reduced, the speed of the critical path is increased and the operating frequency of the semiconductor integrated circuit can be improved.
Claims16
A semiconductor integrated circuit device comprising:
- a first driving circuit comprising a precharge circuit that is controlled by a first clock signal;
- a next gate circuit that receives an output signal provided by the first driving circuit through a transmission line;
- and
- a speed increasing circuit that is controlled by a second clock signal, that detects the change of the output signal of the first driving circuit, that increases the speed of changing the output signal of the first driving circuit and that is connected to the transmission line connecting the next gate circuit to the first driving circuit at a connecting position of the transmission line, wherein a line length between the connecting point and the next gate circuit is shorter than a line length between the connecting point and the first driving circuit, and wherein the output signal of the first driving circuit varies according to input signals of the first driving circuit.
Dependencies are inferred from the claim text.