Method and apparatus for data sampling

A method for sampling input data, comprising:

• providing a base clock having a frequency that is greater than a normal frequency of the input data;
• detecting a level-turning point of the input data in response to the base clock;
• generating responsive to the base clock a plurality of sampling clocks each having a frequency double the normal frequency of the input data and being phase shifted with respect to a corresponding successive sampling clock by one clock period of the base clock;
• selecting one of the plural sampling clocks as a selected sampling clock, so that the selected sampling clock has a first level-turning point synchronized with the level-turning point of the input data and a second level-turning point generated at a middle of a normal cycle of the input data;
• and
• sampling the input data in synchronization with the selected sampling clock.

A data sampling circuit for sampling input data, comprising:

• a clock generator that generates a base clock having a frequency that is n times a normal frequency of the input data, wherein n is an integer greater than zero;
• a sampling clock generator that generates first through nth sampling clocks each having a frequency double the normal frequency of the input data, each of the first though nth sampling clocks being phase shifted with respect to a corresponding successive sampling clock by one clock period of the base clock;
• an edge detector that detects a level-turning point of the input data;
• a clock selector that selects one of the first through nth sampling clocks in response to the level-turning point of the input data;
• and
• a logic circuit that samples the input data in synchronization with the selected sampling clock.

A data sampling circuit, comprising:

• a PLL (Phase Locked Loop) circuit which generates a base clock having a frequency that is greater than a normal frequency of input data;
• an edge detecting circuit which detects a level-turning point of the input data in response to the base clock;
• a sampling clock generating circuit which generates, in response to the base clock, a plurality of sampling clocks each having a frequency double the normal frequency of the input data and being phase shifted with respect to a corresponding successive sampling clock by one clock period of the base clock;
• a clock selecting circuit which selects one of the plural sampling clocks as a selected sampling clock, so that the selected sampling clock has a first level-turning point synchronized with the level-turning point of the input data and a second level-turning point generated at a middle of a normal cycle of the input data;
• and
• a logic circuit that samples the input data in synchronization with the selected sampling clock.