Output buffer circuit of semiconductor integrated circuit

An output buffer circuit of a semiconductor integrated circuit comprising:

• a main driver having a first transistor that increases and decreases current flowing between a signal output terminal and a first power supply line inversely depending on a first control potential, and a second transistor that increases and decreases current flowing between said signal output terminal and a second power supply line depending on a second control potential;
• and
• a predriver that generates said first control potential and said second control potential by employing an input logic signal, and that reduces a speed of increase of the current flowing through said first transistor or said second transistor by prolonging a fall time of said first control potential or a rise time of said second control potential,
• said predriver comprising
• a first inverter having an input terminal connected to said signal output terminal and an output terminal connected to a first node,
• a second inverter having an input terminal connected to said first node and an output terminal connected to a second node,
• a third transistor of the first conductivity type having one end connected to a third power supply line and a control terminal connected to said second node,
• a fourth transistor of the first conductivity type having one end connected to an other end of said third transistor, an other end connected to a third node, and a control terminal connected to said logic signal,
• a fifth transistor of the first conductivity type having one end connected to said third power supply line, an other end connected to said third node, and a control terminal connected to said logic signal,
• a sixth transistor of the second conductivity type having one end connected to a fourth power supply line and a control terminal connected to said first node,
• a seventh transistor of the second conductivity type having one end connected to an other end of said sixth transistor, an other end connected to said third node, and a control terminal connected to said logic signal, and
• an eighth transistor of the second conductivity type having one end connected to said fourth power supply line, an other end connected to said third node, and a control terminal connected to said second node,
• wherein said third node supplies said first control potential to said first transistor.

An output buffer circuit of a semiconductor integrated circuit, comprising:

• a first CMOS inverter having a first pMOS transistor and a first nMOS transistor provided in series between a first power supply line and a first ground line, wherein a connecting point between said first pMOS transistor and said first nMOS transistor is an output of said first CMOS inverter;
• a second CMOS inverter having a second pMOS transistor and a second nMOS transistor provided in series between said first power supply line and said first ground line, wherein a connecting point between said second pMOS transistor and said second nMOS transistor is an output of said second CMOS inverter;
• a main driver having a third pMOS transistor and a third nMOS transistor provided in series between a second power supply line and a second ground line, wherein a gate terminal of said third pMOS transistor is coupled to the output of said first CMOS inverter and wherein a gate terminal of said third nMOS transistor is coupled to the output of said second CMOS inverter;
• a fourth nMOS transistor provided between said first nMOS transistor and said first ground line, a gate terminal of said fourth nMOS transistor is coupled to a gate terminal of said first nMOS transistor;
• and
• a fifth nMOS transistor having a drain connected to said first power supply line, a source connected to a connecting point between said first and fourth nMOS transistors, and a gate terminal connected to the output of said first CMOS inverter.

An output buffer circuit of a semiconductor integrated circuit, comprising:

• a first CMOS inverter having a first pMOS transistor and a first nMOS transistor provided in series between a first power supply line and a first ground line, wherein a connecting point between said first pMOS transistor and said first nMOS transistor is an output of said first CMOS inverter;
• a second CMOS inverter having a second pMOS transistor and a second nMOS transistor provided in series between said first power supply line and said first ground line, wherein a connecting point between said second pMOS transistor and said second nMOS transistor is an output of said second CMOS inverter;
• a main driver having a third pMOS transistor and a third nMOS transistor provided in series between a second power supply line and a second ground line, wherein a gate terminal of said third pMOS transistor is coupled to the output of said first CMOS inverter and wherein a gate terminal of said third nMOS transistor is coupled to the output of said second CMOS inverter;
• a fourth pMOS transistor provided between said second PMOS transistor and said first power supply line, a gate terminal of said fourth pMOS transistor is coupled to a gate terminal of said second pMOS transistor;
• and
• a fifth pMOS transistor having a source connected to said first ground line, a drain connected to a connecting point between said second and fourth pMOS transistors, and a gate connected to the output of said second CMOS inverter.