Input buffer of a semiconductor device that gives only a small scattering in delay time
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorJun Setogawa
Life of this patent
Estimating the term…
Abstract
In a semiconductor memory device, its clock buffer includes a first comparator having a pair of P channel MOS transistors whose gates receive a clock signal and a complementary clock signal, respectively, and a second comparator having a pair of N channel MOS transistors whose gates receive the clock signal and the complementary clock signal, respectively. An internal signal is generated in response to an output signal of the comparator having a shorter response time which starts correspondingly to the cross point where the clock signal and the complementary clock signal cross each other. Even if the level of the cross point is scattered, a scatter in the response time of the internal signal which starts correspondingly to the cross point becomes small.
Claims8
An input buffer of a semiconductor device which generates an internal signal in response to an external signal and supplies the internal signal to an internal circuit, including:
- a first comparator including first and second transistors of first conduction type, input electrodes of which receive said external signal and a reference signal respectively, said first comparator changing a first signal from a first level to a second level in response to the fact that the level of said external signal exceeds the level of said reference signal,
- a second comparator including third and fourth transistors of second conduction type, input electrodes of which receive said external signal and said reference signal respectively, said second comparator changing a second signal from said first level to said second level in response to the fact that the level of said external signal exceeds the level of said reference signal, and
- a logic circuit that changes said internal signal from an inactive level to an active level in response to the fact that either one of said first or second signal turns into a third level between said first and second levels.
An input buffer of a semiconductor device which generates an internal signal in response to an external signal and supplies the internal signal to an internal circuit, including:
- a first comparator including first and second transistors of first conduction type, input electrodes of which receive said external signal and a reference potential respectively, said first comparator comparing the level of said external signal with said reference potential to output a signal having a level corresponding to the comparison result,
- a second comparator including third and fourth transistors of second conduction type, input electrodes of which receive said external signal and said reference potential respectively, said second comparator comparing the level of said external signal with said reference potential to output a signal having a level corresponding to the comparison result, and
- a selection logic circuit that receives output signals of said first and second comparators, selects the output signal of said first comparator when said external signal changes from said first level to said second level, and selects the output signal of said second comparator when said external signal changes from said second level to said first level, so as to change the level of said internal signal in response to the fact that the level of the selected signal changes.
Dependencies are inferred from the claim text.