Programmable logic device input/output architecture with power bus segmentation for multiple I/O standards

A programmable logic device that programmably accommodates a plurality of logic signalling standards having differing power requirements, said programmable logic device comprising:

• programmable logic elements;
• an interconnect structure connecting said programmable logic elements;
• a plurality of input/output terminals;
• a plurality of input/output circuits connected to said interconnect structure and to said input/output terminals, each of said input/output circuits programmably accommodating at least some of said plurality of logic signalling standards and being coupled to a respective one of said input/output terminals for buffering input/output signals between said respective one of said input/output terminals and said programmable logic elements;
• and
• a plurality of power bus conductors;
• wherein:
• when a respective one of said plurality of input/output circuits is operated in accordance with one of said plurality of logic signalling standards, a respective power bus conductor provides power compatible with power requirements of said one of said standards in accordance with which said respective circuit is operated.

A method for operating a programmable logic device that programmably accommodates a plurality of logic signalling standards having differing power requirements, said programmable logic device comprising:

• programmable logic elements,
• an interconnect structure connecting said programmable logic elements,
• a plurality of input/output terminals,
• a plurality of input/output circuits connected to said interconnect structure and to said input/output terminals, each of said input/output circuits programmably accommodating at least some of said plurality of logic signalling standards and being coupled to a respective one of said input/output terminals for buffering input/output signals between said respective one of said input/output terminals and said programmable logic elements, and
• a plurality of power bus conductors;
• said method comprising:
• when one of said plurality of input/output circuits is operated in accordance with one of said plurality of logic signalling standards, providing, through a respective power bus conductor, power compatible with power requirements of said one of said standards in accordance with which circuits in said respective subset are operated.

An integrated circuit comprising:

• an integrated circuit programmable logic device that programmably accommodates a plurality of logic signalling standards having differing power requirements, said integrated circuit programmable logic device comprising:
• programmable logic elements;
• an interconnect structure connecting said programmable logic elements;
• a plurality of input/output terminals;
• a plurality of input/output circuits connected to said interconnect structure and to said input/output terminals, each of said input/output circuits programmably accommodating at least some of said plurality of logic signalling standards and being coupled to a respective one of said input/output terminals for buffering input/output signals between said respective one of said input/output terminals and said programmable logic elements;
• and
• a plurality of power bus conductors, each of said power bus conductors being spatially disposed adjacent a respective subset of said plurality of input/output circuits;
• wherein:
• when circuits in each respective subset of said plurality of input/output circuits are operated in accordance with one of said plurality of logic signalling standards, a respective power bus conductor adjacent each respective subset provides power compatible with power requirements of said one of said standards in accordance with which circuits in said respective subset are operated.