US 6,472,901 B2Granted

Method for in-line testing of flip-chip semiconductor assemblies

AssigneeMicron Technology, Inc.

InventorsChad A. Cobbley, John VanNortwick, Bret K. Street, Tongbi Jiang

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Abstract

Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die-attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection bumps on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of “known good dice” (KGD) rework procedures during repair is eliminated.

Claims7

Dependent claims

A method for in situ electrical testing of a flip-chip semiconductor assembly during its manufacture, the method comprising:

providing one or more integrated circuit (IC) dice, each with a surface having interconnection bumps thereon;
providing a substrate with conductive pads deposited on a surface thereof for flip-chip attachment to said interconnection bumps of said one or more IC dice;
providing a plurality of probes for contacting said substrate;
positioning said one or more IC dice on said surface of said substrate with said interconnection bumps of said one or more IC dice in conductive contact with said conductive pads of said substrate to form said flip-chip semiconductor assembly;
contacting said substrate with said plurality of probes;
while said substrate is in contact with said plurality of probes and said one or more IC dice are positioned on said surface of said substrate, and before sealing of said one or more IC dice, electrically testing said flip-chip semiconductor assembly using said plurality of probes;
repairing said flip-chip semiconductor assembly if it fails said electrical testing, said repairing comprising at least one of:
repairing one or more defective circuit traces on said substrate;
and
repairing one or more defective conductive pads on said substrate;
speed grading said flip-chip semiconductor assembly;
and
sealing said one or more IC dice of said flip-chip semiconductor assembly.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/944,507Filed 30 Aug 2001 · division
Priority: 5 Oct 1998
Published: US 2002/0003434 A110 Jan 2002
Granted: 29 Oct 2002
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G01R 1/0483
Sockets for IC's or transistors: sockets for unleaded IC's having matrix type contact fields, e.g. BGA or PGA devices; Sockets for unpackaged,…
Y10T 29/4913
On flat or curved insulated base, e.g., printed circuit, etc.: assembling to base an electrical component, e.g., capacitor, etc.
Y10T 29/49144
Assembling to base an electrical component, e.g., capacitor, etc.: by metal fusion
G01R
Measuring electric variables

Family

Application09/166,369Parent of this division · filed 5 Oct 1998
Application09/819,472Parent of this division · filed 28 Mar 2001
US 2002/0003434 A1Pre-grant publication · published 10 Jan 2002
US 6,329,832 B1Parent of this division
US 2001/0043077 A1Published application
US 6,545,498 B2Related patent
US 6,472,901 B2This patent

From the US filing history. Foreign family members aren’t listed.