Configuration for testing chips using a printed circuit board

Abstract

A configuration for testing chips includes a printed circuit board having conductive probe needles to electrically connect the printed circuit board to chips and for testing the chips on the printed circuit board in parallel, some of the probe needles configured as dummy needles for mechanically self-aligning the chips. The board is configured closely to the application such that many chips (1) can be tested simultaneously in parallel. The chips can have markings or depressions to be engaged with free ends of the dummy needles remote from the board. Adapters can be disposed between the probe needles and the chips. Also, the chips can have structures disposed thereon between the probe needles and the chips. The board can have alignment aids for orienting the chips.

Dependencies are inferred from the claim text.