Method of calculating parasitic capacitance between electrodes of integrated circuits
AssigneeSamsung Electronics Co., Ltd.
InventorKeun-ho Lee
Life of this patent
Estimating the term…
Abstract
A method of calculating capacitance between conductive patterns of an integrated circuit (IC) by defining a mesh of nodes in a space between at least two electrodes, calculating the electric potential at each node, and then calculating the parasitic capacitance between the electrodes.
Claims13
A method of calculating capacitance between conductive patterns of an integrated circuit (IC) comprising:
- defining a mesh of nodes in space between at least two electrodes;
- calculating the electric potential at each said node;
- and
- calculating the parasitic capacitance between said electrodes from said electric potentials.
A recording medium, for storing program executable by a computer for calculating parasitic capacitance between conductive patterns of a integrated circuit (IC) having at least two electrodes, comprising:
- a module for defining a mesh of nodes in a space between said electrodes;
- a module for calculating the electric potential at each said node;
- and
- a module for calculating the parasitic capacitance between said electrodes from said electric potentials.
A method of calculating parasitic capacitance between electrodes of an integrated circuit (IC) having more than two electrodes to which a predetermined voltage is applied and floating conductive patterns are electrically isolated by an insulating layer between the electrodes, comprising the steps of:
- dividing an electrode structure having the electrodes, the insulating layer, and the floating conductive patterns into a finite mesh, and defining nodes deposed on said mesh;
- obtaining a potential vector using Poisson's equation for each node;
- and
- obtaining a parasitic capacitance between the electrodes from the potential vector.
Dependencies are inferred from the claim text.