Process for realizing an intermediate dielectric layer for enhancing the planarity in semiconductor electronic devices

Abstract

A method is for forming an intermediate dielectric layer to optimize the planarity of electronic devices integrated on a semiconductor which incorporate non-volatile memories. The insulating dielectric is deposited from a liquid state source comprising silicon oxides and organics of the resist type. The liquid dielectric layer is evenly spread by a spinning technique providing good levels of planarity. Solidification, referred to as polymerization, is achieved through a low-temperature thermal cycle. Since this dielectric layer cannot be used as such to isolate the semiconductor substrate from the overlying metallization plane on account of the presence of organics forming a source of impurities, it is arranged for the layer to be encapsulated between two dielectric layers of silicon oxide as deposited from a plasma. To make the highly planarizing intermediate dielectric layer consistent with the other two encapsulating dielectric layers, a rapid annealing step is carried out in an oven under a gas stream, subsequently to the polymerization step. The rapid annealing step is also utilized to densify the upper dielectric layer encapsulating the highly planarizing intermediate dielectric layer.

Dependencies are inferred from the claim text.