Semiconductor device having a shortened wiring length to reduce the size of a chip

A semiconductor device comprising:

• a rectangular interconnection substrate having a first main surface and a second main surface which are opposite to each other;
• a plurality of pad rows which are disposed in parallel with each other over the first main surface of said interconnection substrate and are each formed of a plurality of wire connecting pads along the periphery of said first main surface,
• a plurality of interconnections which are formed on said interconnection substrate and extend in parallel with each other in a direction crossing each row of said plurality of pad rows and are each electrically and commonly connected with one pad row of said plurality of pad rows,
• a plurality of external terminals disposed on the second main surface of said interconnection substrate and electrically connected with said plurality of interconnections, respectively,
• a semiconductor chip being disposed over said first main surface of said interconnection substrate, being formed of a rectangular semiconductor substrate and having, on the main surface thereof, a plurality of bonding pads, and
• a plurality of bonding wires electrically connecting each of said plurality of bonding pads of said semiconductor chip with one of the wire connecting pads commonly connected with each of said plurality of interconnections, for electrically connecting a plurality of bonding pads of said semiconductor chip with each of said plurality of interconnections;
• wherein said plurality of interconnections are formed over the first main surface on which said plurality of wire connecting pads are formed;
• wherein a land row formed of a plurality of lands is disposed between two adjacent pad rows of said plurality of pad rows so as to electrically connect said plurality of external terminals with said plurality of interconnections respectively on said first main surface of said interconnection substrate;
• and
• wherein another land row formed of plural lands is disposed in a region close to a central portion of said first main surface inside of the most inner row of said plurality of pad rows so as to electrically connect, on said first main surface of said interconnection substrate, each of said plurality of external terminals with each of said plurality of interconnections.