US 6,472,727 B2Granted

Semiconductor device and manufacturing method thereof

AssigneesHitachi, Ltd., Hitahi Microcomputer System, Ltd, Hitachi ULSI Engineering Corp.

InventorsChuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe

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Abstract

A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.

Claims20

Dependent claims

A semiconductor device comprising:

a semiconductor chip having a rectangular main surface bounded by first and second sides extending in a first direction, and by third and fourth sides extending in a second direction, perpendicular to said first direction, and having a row of external terminals, extended in the first direction, formed on the main surface;
a first array of bump electrodes formed between the row of external terminals and the first side of the main surface, in a plan view of the main surface;
a second array of bump electrodes formed between the row of external terminals and the second side of the main surface, in the plan view of the main surface;
an elastic layer including a first portion and a second portion,
wherein the first portion of the elastic layer is interposed between the first array of bump electrodes and the main surface of the semiconductor chip, and the second portion of the elastic layer is interposed between the second array of bump electrodes and the main surface of the semiconductor chip;
first wirings, formed on the first portion of the elastic layer, electrically connecting the first array of bump electrodes with the row of external terminals;
and
second wirings, formed on the second portion of the elastic layer, electrically connecting the second array of bump electrodes with the row of external terminal,
wherein the first portion of the elastic layer covers a continuous area over a part of the main surface of the chip and is bounded, in the second direction, by first and second ends thereof, the first and second ends of said first portion are extended in the first direction, the first end is located between the first array of bump electrodes and the row of external terminals, in the plan view, and the second end is opened, and
wherein the second portion of the elastic layer covers a continuous area over another part of the main surface of the chip and is bounded, in the second direction, by first and second ends thereof, the first and second ends of said second portion are extended in the first direction, the first end thereof is located between the second array of bump electrodes and the row of external terminals, in the plan view, and the second end thereof is opened.

7 more elements

A semiconductor device comprising:

a semiconductor chip having a rectangular main surface bounded by first and second sides extending in a first direction, and by third and fourth sides extending in a second direction, perpendicular to said first direction, and having a row of external terminals, extended in the first direction, formed on the main surface;
a first array of bump electrodes formed between the row of external terminals and the first side of the main surface, in a plan view of the main surface;
a second array of bump electrodes formed between the row of external terminals and the second side of the main surface, in the plan view of the main surface;
an elastic layer including a first portion and a second portion,
wherein the first portion of the elastic layer is interposed between the first array of bump electrodes and the main surface of the semiconductor chip, and the second portion of the elastic layer is interposed between the second array of bump electrodes and the main surface of the semiconductor chip;
first wirings, formed on the first portion of the elastic layer, electrically connecting the first array of bump electrodes with the row of external terminals;
and
second wirings, formed on the second portion of the elastic layer, electrically connecting the second array of bump electrodes with the row of external terminals;
wherein the first portion of the elastic layer covers a continuous area over a part of the main surface of the chip and is bounded, in the second direction, by first and second ends thereof, the first and second ends of said first portion are extended in the first direction, the first end is located between the first array of bump electrodes and the row of external terminals, in the plan view, and the second end is not covered with sealant, and
wherein the second portion of the elastic layer covers a continuous area over another part of the main surface of the chip and is bounded, in the second direction, by first and second ends thereof, the first and second ends of said second portion are extended in the first direction, the first end thereof is located between the second array of bump electrodes and the row of external terminals, in the plan view, and the second end thereof is not covered with sealant.

7 more elements

An electronic device having a semiconductor device and a mounting substrate, the semiconductor device comprising:

a semiconductor chip having a rectangular main surface bounded by first and second sides extending in a first direction, and by third and fourth sides extending in a second direction, perpendicular to said first direction, and having a row of external terminals formed on the main surface;
a first array of bump electrodes formed between the row of external terminals and the first side of the main surface, in a plan view of the main surface;
a second array of bump electrodes formed between the row of external terminals and the second side of the main surface, in the plan view of the main surface;
an elastic layer including a first portion and a second portion,
wherein the a first portion of the elastic layer is interposed between the first array of bump electrodes and the main surface of the semiconductor chip, and the second portion of the elastic layer is interposed between the second array of bump electrodes and the main surface of the semiconductor chip;
first wirings, formed on the first portion of the elastic layer, electrically connecting the first array of bump electrodes with the row of external terminals;
and
second wirings, formed on the second portion of the elastic layer, electrically connecting the second array of bump electrodes with the row of external terminals;
wherein the first portion of the elastic layer covers a continuous area over a part of the main surface of the chip and is bounded, in the second direction, by first and second ends thereof, the first and second ends of said first portion are extended in the first direction, the first end is located between the first array of bump electrodes and the row of external terminals, in the plan view, and the second end is not covered with sealant, and
wherein the second portion of the elastic layer covers a continuous area over another part of the main surface of the chip and is bounded, in the second direction, by first and second ends thereof, the first and second ends of said second portion are extended in the first direction, the first end thereof is located between the second array of bump electrodes and the row of external terminals, in the plan view, and the second end thereof is not covered with sealant,
wherein the mounting substrate is connected with the semiconductor device via the bump electrodes, and
wherein the semiconductor chip has a heat expansion coefficient different from that of the mounting substrate.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/771,648Filed 30 Jan 2001 · continuation
Priority: JP 8-6663722 Mar 1996
Published: US 2001/0005055 A128 Jun 2001
Granted: 29 Oct 2002
Term ends: Not estimatedThe source records don’t support an estimate.

Classification20 codes

H10W 90/701
Package configurations: characterised by the relative positions of pads or connectors relative to package parts
H10W 70/635
Vias, e.g. via plugs: through-vias
H10W 70/688
Characterised by their insulating layers or insulating parts: flexible insulating substrates
H10W 72/01551
Of bond wires: changing the shapes of bond wires

Family

Application08/822,933Parent of this continuation · filed 21 Mar 1997
Application09/449,834Parent of this continuation · filed 26 Nov 1999
US 2001/0005055 A1Pre-grant publication · published 28 Jun 2001
US 6,342,726 B2Parent of this continuation
US 2001/0035575 A1Published application
US 6,472,727 B2This patent

From the US filing history. Foreign family members aren’t listed.