US 6,472,721 B2Granted

Dual damascene interconnect structures that include radio frequency capacitors and inductors

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsSsu-Pin Ma, Chun-Hon Chen, Ta-Hsun Yeh, Kuo-Reay Peng, Heng-Ming Hsu, Kong-Beng Thei, Chi-Wu Chou, Yen-Shih Ho

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Abstract

In many mixed-signal or radio frequency Rf applications, inductors and capacitors are needed at the same time. For a high performance inductor devices, a thick metal layer is needed to increase performance, usually requiring an extra masking process. The present invention describes both a structure and method of fabricating both copper metal-insulator-metal (MIM) capacitors and thick metal inductors, simultaneously, with only one mask, for high frequency mixed-signal or Rf, CMOS applications, in a damascene and dual damascene trench/via process. High performance device structures formed by this invention include: parallel plate capacitor bottom metal (CBM) electrodes and capacitor top metal (CTM) electrodes, metal-insulator-metal (MIM) capacitors, thick inductor metal wiring, interconnects and contact vias.

Claims13

Dependent claims

A parallel plate capacitor and thick metal inductor structure comprising:

(a) a semiconductor substrate or IC module, having a layer of dielectric;
(b) an underlying metal diffusion barrier layer and overlying a first level conductor wiring metal formed in said dielectric layer;
(c) a metal protect buffer layer formed over said first level conductor wiring layer;
(d) an intermetal dielectric (IMD) layer formed over said metal protect buffer layer;
(e) a plurality of metal-insulator-metal MIM/Inductor damascene area openings selectively formed in beth said intermetal dielectric (IMD) layer and in said metal protect buffer layer;
(f) a passivating insulating protect buffer layer formed over said intermetal dielectric and over exposed first level conductor wiring;
(g) an MIM insulating layer formed over said insulating protect buffer layer;
(h) a conductive metal protect buffer layer formed over said MIM insulating layer;
(i) dual damascene via/trench openings selectively formed in said intermetal dielectric (IMD) layer;
(j) conducting inlaid thick metal for high performance formed in all openings to form dual damascene trench interconnects, contact vias, and metal-insulator-metal (MIM) capacitor top metal (CTM) electrodes/inductor thick metal line structures.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/963,749Filed 27 Sep 2001 · division
Priority: 24 Jul 2000
Published: US 2002/0019123 A114 Feb 2002
Granted: 29 Oct 2002
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10D 1/68
Capacitors: capacitors having no potential barriers
H10D 1/692
Capacitors having no potential barriers: electrodes
H10D 1/684
Having dielectrics comprising perovskite structures: the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or…
H10D 1/716
Having non-planar surfaces, e.g. formed by texturisation: having vertical extensions