Semiconductor device with a well wherein a scaling down of the layout is achieved
AssigneesMitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Company Limited
InventorsFutoshi Igaue, Katsumi Dosaka
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Abstract
A shallow P well and a deep P well are formed in the surface of a P type semiconductor substrate so as to partially overlap each other and these wells are surrounded by an N well, a deep bottom N type well and a connection N well. The impurity concentration of this overlapping region is higher than the impurity concentration of the P well or of the deep P well and a P+ type region is formed in the surface of the overlapping region. A potential (VBB) different from the ground potential is applied to the P+ type region. The P+ type region is formed in overlapping region and, thereby, the layout of the semiconductor device can be scaled down.
Claims16
A semiconductor device comprising:
- a semiconductor substrate of a first conductive type having a main surface;
- a first well region of the first conductive type that is formed of a predetermined depth in said main surface of said semiconductor substrate and wherein first semiconductor elements are provided;
- a second well region of the first conductive type that is formed in said main surface of said semiconductor substrate so as to partially overlap an edge part of said first well region, that is shallower than said first well region and wherein second semiconductor elements are provided;
- and
- a first voltage application part that is formed in a region where said first well region and said second well region overlap and to which a voltage for fixing said first well region and said second well region at a predetermined potential is applied.
A semiconductor device comprising:
- a semiconductor substrate of a first conductive type having a main surface;
- a first well region of the first conductive type formed of a predetermined depth in the main surface of said semiconductor substrate;
- a voltage application part that is formed in said first well region and to which a voltage for fixing said first well region at a predetermined potential is applied;
- and
- a second well region of a second conductive type that is formed in said main surface of said semiconductor substrate so as to adjoin said first well region and that is deeper than said first well region, wherein
- a deeply located part of said second well region on the side of said first well region is recessed in the direction away from said first well region.
Dependencies are inferred from the claim text.