Trench DMOS transistor structure having a low resistance path to a drain contact located on an upper surface

A semiconductor device comprising;

• a first uniformly doped substrate region of semiconductor material, doped to a first concentration with a dopant of a first conductivity type;
• a gate trench formed within said first uniformly doped substrate region, said gate trench having sides and a bottom;
• a drain access trench formed within said first uniformly doped substrate region, said drain access trench having sides and a bottom;
• a second region of semiconductor material located within said first uniformly doped substrate region and adjacent to said gate trench near said bottom of said rate trench and extending adjacent to said drain access trench near said bottom of said drain access trench, said second region being of said first conductivity type and having a higher dopant concentration than said first uniformly doped substrate region, and said second region formed of two overlapping regions, one region diffused through the bottom of said gate trench and one region diffused through the bottom of said drain access trench;
• a gate electrode within said gate trench;
• a layer of gate dielectric material insulating said state electrode from said first uniformly doped substrate region and second regions;
• a drain region of semiconductor material located within said drain access trench, said drain region being of said first conductivity type and having a higher dopant concentration than said first uniformly doped substrate region;
• a source region formed on the surface of said first uniformly doped substrate region;
• and
• a body region within said first region surrounding said source region, said body region having a second conductivity type opposite said first conductivity type.