Chemical vapor deposition process
AssigneeMicron Technology, Inc.
InventorsAnand Srinivasan, Sujit Sharon, Raj Narasimhan
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AssigneeMicron Technology, Inc.
InventorsAnand Srinivasan, Sujit Sharon, Raj Narasimhan
Estimating the term…
The present invention relates to chemical vapor deposition processes related to the manufacture of integrated circuit devices. In accordance with one embodiment of the present invention, a process for forming an electrical contact to a silicon substrate is provided wherein a semiconductor wafer is positioned in a reaction chamber wherein the semiconductor wafer includes an insulating layer disposed over a semiconductor substrate, and the insulating layer defines a contact opening therein. The contact opening defines insulating side wall regions herein. The insulating side walls extend from an upper surface region of the insulating layer to an exposed semiconductor region of the semiconductor substrate. A set of reactants are introduced into the reaction chamber, RF plasma is generated in the vicinity of the semiconductor wafer, and the temperature and pressure of the reaction chamber is regulated. The introduction of the reactants, the generation of the RF plasma, and the regulation of the temperature and pressure is controlled so as to form a primary film over the upper surface region of the insulating layer, over the insulating side wall regions, and over the exposed semiconductor region of the semiconductor substrate. A nitrogen-based gas is introduced into the reaction chamber and a nitridizing RF plasma is generated in the vicinity of the semiconductor wafer so as to nitridize the primary film formed over the upper surface region, the insulating side wall regions, and the exposed semiconductor region. An electrical contact is formed in the contact opening.
A chemical vapor deposition process, wherein a semiconductor wafer is positioned in a reaction chamber, said process comprising:
A chemical vapor deposition process as claimed in 5, wherein said nitridizing process causes said primary film formed over said exposed silicon region to be passivated with a layer of TiN.
A chemical vapor deposition process, wherein a semiconductor wafer is positioned in a reaction chamber, said semiconductor wafer including an insulating layer disposed over a semiconductor substrate and said insulating layer defining a contact opening therein, said contact opening defining insulating side wall regions therein, said insulating side walls extending from an upper surface region of said insulating layer to an exposed semiconductor region of said semiconductor substrate, said process comprising:
A chemical vapor deposition process, wherein a semiconductor wafer is positioned in a reaction chamber, said process comprising:
A chemical vapor deposition process, wherein a semiconductor wafer is positioned in a reaction chamber, said process comprises:
Dependencies are inferred from the claim text.