US 6,472,308 B1Granted

Borderless vias on bottom metal

AssigneeAdvanced Micro Devices, Inc.

InventorSunil D. Mehta

Life of this patent

Estimating the term…

Abstract

An improved manufacturing process and an improved device made by the process for forming via interconnects between metal layers in a multilevel metallization structure substantially eliminates trench formation during via overetch and exploding vias during via fill. An insulating multilayer structure comprising a conformal oxide, a spin-on layer, and an etch stop layer for the via etch locally planarizes the region adjacent to metal lines before the ILD is deposited and vias are patterned and etched. Using this process, metal borders around vias can be reduced or eliminated, thereby increasing circuit packing density.

Claims16

Dependent claims

An integrated circuit manufacturing process for fabricating a borderless via for interconnecting a first bottom metal line to a second top metal line in a multilevel metallization structure on a semiconductor substrate, said first bottom metal line having a top conducting surface, comprising the steps of:

providing a semiconductor substrate having devices therein to be connected, having an insulating layer on said substrate, and having a bottom metal layer deposited onto said insulating layer on said substrate;
patterning and etching said bottom metal layer to provide said first bottom metal line having an exposed top conducting surface and an edge surface, and to expose portions of said insulating layer;
forming a dielectric layer surrounding said bottom metal line, said dielectric layer having a top dielectric surface substantially locally planar with said top conducting surface of said bottom metal line near said bottom metal line;
depositing a non-conducting via etch stop layer onto said top conducting surface of said bottom metal line and said top dielectric surface;
depositing an ILD layer onto said via etch stop layer;
etching a via having a first and a second portion through said ILD layer to expose the region of said via etch stop layer under said via, said via etch stop layer being substantially unetched by said via etch, said first via portion being atop said via etch stop layer atop said bottom metal line, and said second via portion being atop said via etch stop layer atop said dielectric layer, said via having a bottom surface and a side surface;
removing said exposed region of said via etch stop layer to expose the region of said top conducting surface of said bottom metal line and the region of said top dielectric surface under said via;
depositing a barrier/nucleation/adhesion layer onto said via side surface and onto said exposed portion on said top conducting surface of said bottom metal line and said top dielectric surface;
and
filling said via with a conductive material wherein during said via filling step said top surface and said edge surface of said bottom metal line are protected by intervening layers from exposure to reactants and reaction products of said via filling step.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/949,276Filed 7 Sep 2001 · division
Priority: 21 Nov 1996
Granted: 29 Oct 2002
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
H10W 20/0693
By forming self-aligned vias or self-aligned contact plugs: by forming self-aligned vias
H10W 20/074
Of dielectric parts thereof: of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or…
H10W 20/092
Of dielectric parts thereof: by smoothing the dielectric parts

Family

Application08/754,564Parent of this division · filed 21 Nov 1996
US 6,362,527 B1Parent of this division
US 6,472,308 B1This patent

From the US filing history. Foreign family members aren’t listed.

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Abstract

providing a semiconductor substrate having devices therein to be connected, having an insulating layer on said substrate, and having a bottom metal layer deposited onto said insulating layer on said substrate;
patterning and etching said bottom metal layer to provide said first bottom metal line having an exposed top conducting surface and an edge surface, and to expose portions of said insulating layer;
forming a dielectric layer surrounding said bottom metal line, said dielectric layer having a top dielectric surface substantially locally planar with said top conducting surface of said bottom metal line near said bottom metal line;
depositing a non-conducting via etch stop layer onto said top conducting surface of said bottom metal line and said top dielectric surface;
depositing an ILD layer onto said via etch stop layer;
etching a via having a first and a second portion through said ILD layer to expose the region of said via etch stop layer under said via, said via etch stop layer being substantially unetched by said via etch, said first via portion being atop said via etch stop layer atop said bottom metal line, and said second via portion being atop said via etch stop layer atop said dielectric layer, said via having a bottom surface and a side surface;
removing said exposed region of said via etch stop layer to expose the region of said top conducting surface of said bottom metal line and the region of said top dielectric surface under said via;
depositing a barrier/nucleation/adhesion layer onto said via side surface and onto said exposed portion on said top conducting surface of said bottom metal line and said top dielectric surface;
and
filling said via with a conductive material wherein during said via filling step said top surface and said edge surface of said bottom metal line are protected by intervening layers from exposure to reactants and reaction products of said via filling step.

7 more elements

Facts

Application

09/949,276Filed 7 Sep 2001 · division

Priority

21 Nov 1996

Granted

29 Oct 2002

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
H10W 20/0693
By forming self-aligned vias or self-aligned contact plugs: by forming self-aligned vias
H10W 20/074
Of dielectric parts thereof: of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or…
H10W 20/092
Of dielectric parts thereof: by smoothing the dielectric parts