Planarization process to achieve improved uniformity across semiconductor wafers

A method for planarizing a dielectric layer on a semiconductor wafer while eliminating a mask and an etch step, comprising the steps of:

• providing a semiconductor wafer having first areas and second areas, the first areas including trenches formed in a substrate of the semiconductor wafer;
• depositing and sputtering on two dielectric layers on the semiconductor wafer to fill the trenches whereby up features form in the second areas, wherein a volume difference of dielectric material between the first areas and the second areas is reduced by biasing a deposition process for at least one of the two layers;
• adjusting the sputtering of the dielectric layer after the trenches are filled to provide uniformity between a height of the dielectric layer in the first areas and a height of the dielectric layer in the second areas;
• polishing an edge portion of the semiconductor wafer to remove a portion of the dielectric layer by exerting a bias force against the edge portions of the wafer during polishing;
• and
• polishing the dielectric layer across the entire semiconductor wafer by employing a single non-stacked polishing pad and a slurry to planarize the first areas and the second areas wherein a mask step and an etch step are eliminated from the polishing step wherein the polishing is performed down to an etch stop layer.

A method for planarizing a dielectric layer on a semiconductor wafer while eliminating a mask and etch step, comprising the steps of:

• providing a semiconductor wafer having an array area including trenches formed in a substrate of the semiconductor wafer;
• depositing and sputtering on a first oxide layer on the semiconductor wafer to fill the trenches to form trench isolation regions;
• depositing and sputtering a second oxide layer on the first dielectric layer at a different bias power than the first oxide layer to bring a combined height of the first oxide layer and the second oxide layer over the array region closer to a combined height of the first oxide layer and the second oxide layer for up features;
• polishing an edge portion of the semiconductor wafer to remove a portion of the first and second oxide layers by exerting a bias force against the edge portions of the wafer during polishing;
• and
• polishing the dielectric layer across the entire semiconductor wafer by employing a single non-stacked polishing pad and a slurry to planarize the first and second oxide layers wherein a mask step and etch step are eliminated from the polishing process wherein the polishing is performed down to and etch stop layer.