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US 6,472,266 B1Granted
Method to reduce bit line capacitance in cub drams
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChih-Hsing Yu, Yu-Shen Chen
Life of this patent
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Abstract
A new method is provided for the creation of the bit line contact plug. CUB capacitors typically are located adjacent to the bit line contact plug, a parasitic capacitance therefore exists between the CUB and the contact plug. Typical interface between the CUB and the bit line contact plug consists of a dielectric. By creating an air gap that partially replaces the dielectric between the CUB and the bit line contact plug, the dielectric constant of the interface between the bit line and the CUB is reduced, thereby reducing the parasitic coupling between the bit line contact plug and the CUB. This enables the creation of CUB capacitors of increased height, making the CUB and the therewith created DRAM devices better suited for the era of sub-micron device dimensions.
Claims21
A method of fabricating a bit line for a DRAM device on a semiconductor substrate, wherein a top portion of a bit line contact hole is provided with an air gap, comprising the steps of:
- providing a semiconductor substrate, an active surface region having been defined and being bounded by Shallow Trench Isolation regions in the surface of said substrate, two gate structures having been provided on the active surface region of the substrate overlying a gate insulation layer, with two source regions and a drain region having been provided in the surface of said substrate self-aligned with and at the sides of and between the two gate structures, said drain region forming a bit line contact in the surface of said substrate, said two source regions forming storage node contacts in the surface of said substrate;
- depositing a first layer of dielectric over the surface of the substrate, including the surface of said two gate structures provided over the active surface region of the substrate;
- depositing a layer of etch stop material over the surface of said first layer of dielectric;
- creating capacitors overlying said storage node contact points provided in the surface of said substrate, said creating capacitors comprising creating a first conductive plug overlying and being in contact with said bit line contact provided in the surface of said substrate;
- creating a second conductive plug overlying said first conductive plug, said second conductive plug being surrounded by said air gap, said air gap being formed between the second conductive plug and material surrounding the second conductive plug;
- closing said air gap surrounding said second conductive plug, said closing said air gap comprising:
- (i) deposition of a layer of oxide;
- and
- (ii) polishing the surface of said deposited layer of oxide;
- and providing interconnect metal to said second conductive plug.
7 more elements
A method of fabricating a bit line for a DRAM device on a semiconductor substrate, Capacitor Under Bit Line (CUB) capacitors being part of said DRAM device, wherein a top portion of a bit line contact hole for said DRAM device is provided with an air gap, comprising the steps of:
- providing a semiconductor substrate, an active surface region having been defined and being bounded by Shallow Trench Isolation regions in the surface of said substrate, two gate structures having been provided on the active surface region of the substrate overlying a gate insulation layer, with two source regions and a drain region having been provided in the surface of said substrate self-aligned with and at the sides of and between the two gate structures, said drain region being located between said two gate structures, said two source regions between located between said two gate structures and said regions of STI, said drain region forming a bit line contact in the surface of said substrate, said two source regions forming storage node contacts in the surface of said substrate;
- depositing a first layer of dielectric over the surface of the substrate, including the surface of said two gate structures provided over the active surface region of the substrate;
- depositing a layer of etch stop material over the surface of said first layer of dielectric;
- patterning and etching said etch stop layer and said first layer of dielectric, creating an opening in the etch stop layer and the first layer of dielectric that aligns with the bit line contact provided on the surface of the substrate, further creating two openings in the etch stop layer and the first layer of dielectric that align with the storage node contact provided in the surface of the substrate;
- depositing a layer of polysilicon over the surface of the etch stop layer, filling the openings created in the etch stop layer and the first layer of dielectric with polysilicon;
- polishing the deposited layer of polysilicon down to the surface of the etch stop layer, creating conductive plugs through the etch stop layer and first layer of dielectric for storage node contacts and bit line contact;
- depositing a second layer of dielectric over the surface of the etch stop layer, including the surface of the conductive plugs that have been created through the etch stop layer and the first layer of dielectric;
- creating a patterned first layer of photoresist over the surface of the second layer of dielectric, the pattern of openings created in the first layer of photoresist second layer of dielectric aligning with the storage node contacts provided in the surface of the substrate;
- etching the second layer of dielectric in accordance with the openings that have been created in the first layer of photoresist, exposing the surface of the storage node contacts created in the first layer of dielectric;
- removing the patterned first layer of photoresist from the surface of the second layer of dielectric, exposing the surface of the second layer of dielectric;
- depositing a first electrode material over the surface of the second layer of dielectric, including inside surfaces of the openings created in the second layer of dielectric;
- polishing the surface of the deposited first electrode material down to the surface of the second layer of dielectric, completing the creation first electrodes of the CUB capacitors;
- depositing a layer of capacitor dielectric over the surface of the second layer of dielectric, including the surface of the created first electrodes of the CUB capacitors;
- depositing a second electrode material over the exposed surface of the second layer of dielectric, including the surface of said capacitor dielectric;
- patterning and etching the layer of second electrode material, creating an opening through said layer of second electrode material that align with said bit line contact, creating second electrodes of the CUB capacitors;
- etching through the second layer of dielectric in a pattern of said opening created through said second electrode material, stopping on the surface of the etch stop layer, creating an opening in the second layer of dielectric, exposing the surface of the bit line contact plug created in the first layer of dielectric, leaving in place a layer of second dielectric between the first electrodes of the CUB capacitors and the sidewalls of the opening that is created in the second layer of dielectric;
- depositing a layer of F-poly over the surface of the second electrodes of the CUB capacitors, including the surface of the layer of first dielectric that has been left in place over the sidewalls of the opening created in the second layer of dielectric;
- removing the layer of F-poly from the surface of the second electrodes of the CUB capacitors, leaving in place a layer of F-poly over the layer of second dielectric left in place between the first electrodes of the CUB capacitors and the sidewalls of the opening that has been created in the second layer of dielectric;
- depositing a layer of LPTEOS over the surface of the second electrodes of the CUB capacitors, including the surface of the layer of F-poly that has been over the sidewalls of the opening created in the second layer of dielectric;
- removing the layer of LPTEOS from the surface of the second electrodes of the CUB capacitors, leaving in place a layer of LPTEOS over the layer of F-poly that has been created on the sidewalls of the opening that has been created in the second layer of dielectric;
- depositing a layer of D-poly over the surface of the second electrode of said CUB capacitors, filling the opening created in the second layer of dielectric is with D-poly;
- removing the layer of D-poly from the surface of the second electrodes of the CUB capacitors, forming a conductive plug through the second layer of dielectric;
- removing the layer of LPTEOS from the opening created in the second layer of dielectric;
- depositing a layer of PETEOS over the surface of the second electrode of the CUB capacitors, including the surface of the opening created in the second layer of dielectric, closing the opening created in the second layer of dielectric;
- polishing the surface of the deposited layer of PETEOS, leaving in place a layer of PETEOS having a measurable thickness over the surface of said second layer of dielectric, including the surface of the opening created in said second layer of dielectric;
- patterning the layer of PETEOS, creating an opening in the layer of PETEOS that aligns with the conductive plug formed through the second layer of dielectric;
- depositing a layer of metal over the surface of the layer of PETEOS, filling the opening created in the layer of PETEOS with metal;
- polishing the layer of metal deposited on the surface of the layer of PETEOS, leaving in place a layer of metal having a measurable thickness over the surface of said layer of PETEOS;
- and
- patterning the deposited layer of metal, creating interconnect metal to the bit line of the DRAM cell.
27 more elements
Dependencies are inferred from the claim text.