Negative resistance memory cell and method
AssigneeMicron Technology, Inc.
InventorWendell P. Noble
Life of this patent
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Abstract
A SRAM memory cell including two tunnel diodes coupled in series and a MOS FET. first of the tunnel diodes may be formed in a shallow trench. A second of the tunnel diodes may be formed in a source or drain contact region of the FET. The FET acts as a pass gate to allow data to be read from or written to the memory cell when the gate of the FET is biased to turn the FET ON. The FET otherwise acts to prevent the datum stored in the memory cell from being altered when the FET is turned OFF. The memory cell may be formed to be unusually compact and has a reduced power supply requirements compared to conventional SRAM memory cells. As a result, a compact and robust SRAM having reduced standby power requirements is realized.
Claims16
A method for forming a memory cell in a substrate, comprising:
- forming an active region in the substrate;
- forming a trench in the substrate to isolate the active regions;
- forming in the active region a switch having a source/drain region;
- forming a first negative resistance device in the trench coupled to the source/drain region;
- and
- forming a second negative resistance device in the source/drain region.
A method for forming a memory cell in a substrate, comprising:
- forming a trench in the substrate;
- forming a first negative resistance device in the trench forming a switch having a source/drain region formed in the substrate, the source/drain region abutting the trench and coupled to the first negative resistance device;
- and
- forming a second negative resistance device in the source/drain region.
A method for forming a negative resistance memory in a silicon substrate, comprising:
- forming a shallow trench in the silicon substrate;
- forming a first negative resistance device in the shallow trench, the first negative resistance device having first and second electrodes, the first electrode being coupled to a first reference voltage;
- forming a second negative resistance device in the silicon substrate, the second negative resistance device having a first electrode coupled to a second reference voltage and a second electrode coupled to the second electrode of the first negative resistance device;
- and
- forming a switching element on the silicon substrate, the switching element having a control electrode coupled to a first selection line, a first current-carrying electrode coupled to the second electrodes of the first and second negative resistance devices, and a second current-carrying electrode coupled to a second selection line.
Dependencies are inferred from the claim text.