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US 6,472,261 B2Granted
Method of forming an integrated circuit contact structure having gate electrode protection for self-aligned contacts with zero enclosure
AssigneeSTMicroelectronics S.r.l.
InventorLoi N. Nguyen
Life of this patent
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Abstract
A technique for forming integrated circuit device contacts includes the formation of nitride spacers along side gate electrodes for LDD definition. In addition, a nitride cap layer is formed over the gate electrodes. When a contact opening is formed through the interlevel oxide dielectric, the nitride cap and sidewall spacers protect the gate electrode from damage and shorting. A highly doped poly plug is formed in the opening to make contact to the underlying substrate. Metalization is formed over the poly plug in the usual manner.
Claims16
A method for forming a contact in an integrated circuit device, comprising:
- forming a gate electrode on a substrate surface, the gate electrode having a capping layer of a first material on an upper surface of the gate electrode leaving sides of the electrode exposed;
- forming sidewalls alongside the gate electrode, the sidewalls including:
- a first region of a second material selectively etchable over the first material and formed to a selected thickness on both a side of the gate electrode and the substrate surface adjacent the gate electrode, and
- a second region of the first material on the second material formed on the first region alongside the gate electrode and over the substrate surface,
- wherein the first region of each sidewall is an L-shaped oxide layer formed by reoxidizing the substrate and the exposed sides of the gate electrode;
- forming an interlevel dielectric layer of the second material over the gate electrode, sidewalls, and substrate;
- etching an opening through the interlevel dielectric layer to expose a portion of the substrate, wherein the gate electrode is protected by the sidewalls and the capping layer;
- forming a conductive plug in the opening in contact with the exposed portion of the substrate by:
- depositing a conductive material over the interlevel dielectric layer and filling the opening;
- and
- etching back the conductive material to form a plug having an upper surface approximately coplanar with an upper surface of the interlevel dielectric layer;
- and forming an interconnect over the interlevel dielectric and the conductive plug.
9 more elements
A method of forming a contact opening, comprising:
- forming a gate electrode on a substrate;
- forming a capping layer of a first material on the gate electrode, wherein the first material is selectively etchable over a second material and the second material is selectively etchable over the first material;
- forming an L-shaped etch stop layer of the second material on sidewalls of the gate electrode and on a surface of the substrate adjacent the gate electrode by reoxidizing the substrate and the exposed sides of the gate electrode;
- forming a layer of the first material over the gate electrode and the surface of the substrate adjacent the gate electrode;
- patterning the layer of the first material;
- etching an opening through the layer of the second material to expose a portion of the substrate, wherein the patterned layer of the first material and a portion of the etch stop layer remaining after etching the opening form a sidewall alongside the gate electrode;
- and
- forming a conductive plug in the opening in contact with the exposed portion of the substrate by:
- depositing a conductive material over the interlevel dielectric layer and filling the opening;
- and
- etching back the conductive material to form a plug having an upper surface approximately coplanar with an upper surface of the interlevel dielectric layer.
8 more elements
A method of forming a contact, comprising:
- forming a plurality of gates spaced apart on a substrate, each gate including a nitride capping layer on a polysilicon gate electrode and a gate dielectric, the nitride capping layer leaving sides of the gate electrode and gate dielectric exposed;
- reoxidizing the substrate and the exposed sides of the polysilicon gate electrode to form an L-shaped oxide layer to a selected thickness on both sidewalls of each gate electrode and on a surface of the substrate between the gate electrodes;
- forming nitride sidewall regions alongside the gates and over the oxide layer;
- forming an oxide interlevel dielectric over the gates, the sidewall regions, and the surface of the substrate between the gates;
- etching an opening through the oxide interlevel dielectric and the oxide layer over the surface of the substrate between the gates to expose a portion of the substrate;
- and
- forming a contact within the opening by:
- depositing a conductive material over the interlevel dielectric layer and filling the opening;
- and
- etching back the conductive material to form a plug having an upper surface approximately coplanar with an upper surface of the interlevel dielectric layer.
7 more elements
Dependencies are inferred from the claim text.