Failure analysis method for chip of ball grid array type semiconductor device
AssigneeNEC Corporation
InventorTadashi Ozawa
Life of this patent
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Abstract
In a failure analysis method for a ball grid array type semiconductor device including a semiconductor chip having pads, first solder balls, an interposer substrate and second solder balls, the second solder balls and the interposer substrate are removed from the semiconductor device, and then, the first solder balls are removed from the semiconductor device. Then, the semiconductor device is mounted on a package, and a wire bonding operation is performed between the pads of the semiconductor chip and bonding pads of the package. Finally, a test operation is performed upon the semiconductor chip by mounting the package on a tester.
Claims13
A failure analysis method for a ball grid array type semiconductor device comprising a semiconductor chip having pads, first solder balls formed on said pads, an interposer substrate formed on said first semiconductor balls and second solder balls formed on said interposer substrate, comprising the steps of:
- removing said second solder balls and said interposer substrate from said semiconductor device;
- removing said first solder balls from said semiconductor device to expose said pads on a surface of said semiconductor chip, after said second solder balls and said interposer substrate are removed;
- mounting said semiconductor device on a package, after said first solder balls are removed and said pads exposed;
- performing a wire bonding operation on said pads of said semiconductor chip and on bonding pads of said package to connect bonding wires therebetween;
- and
- performing a test operation upon said semiconductor chip by mounting said package on a tester.
A failure analysis method for a ball grid array type semiconductor device comprising a semiconductor chip having pads on a front surface thereof, first solder balls formed on said pads, an interposer substrate formed on said first semiconductor balls, second solder balls formed on said interposer substrate and a heat spreader adhered to a back surface of said semiconductor chip, comprising the steps of:
- removing said heat spreader;
- removing said second solder balls and said interposer substrate from said semiconductor device, after said heat spreader is removed;
- removing said first solder balls from said semiconductor device to expose said pads on a surface of said semiconductor chip, after said second solder balls and said interposer substrate are removed;
- mounting said semiconductor device on a package, after said first solder balls are removed and said pads exposed;
- performing a wire bonding operation on said pads of said semiconductor chip and bonding pads of said package;
- and
- performing a test operation upon said semiconductor chip by mounting said package on a tester.
A failure analysis method for a ball grid array type semiconductor device comprising a semiconductor chip having pads on a front surface thereof, first solder balls formed on said pads, an interposer substrate formed on said first semiconductor balls, second solder balls formed on said interposer substrate and a heat spreader adhered to a back surface of said semiconductor chip, comprising the steps of:
- removing said second solder balls and said interposer substrate from said semiconductor device;
- removing said heat spreader, after said second solder balls and said interposer substrate;
- removing said first solder balls to exposed said pads, after said heat spreader is removed;
- mounting said semiconductor device on a package, after said first solder balls are removed;
- performing a wire bonding operation on said pads of said semiconductor chip and on bonding pads of said package;
- and
- performing a test operation upon said semiconductor chip by mounting said package on a tester.
Dependencies are inferred from the claim text.