Semiconductor device and method of fabricating the same

A semiconductor device comprising:

• a substrate having an insulating surface;
• a semiconductor layer formed over the substrate;
• a gate insulating film being in contact with the semiconductor layer;
• a gate electrode being in contact with the gate insulating film;
• and
• a gate wiring line connected to the gate electrode,
• wherein the gate electrode includes a first conductive layer being in contact with the gate insulating film,
• wherein the gate wiring line includes a region made of the first conductive layer and a second conductive layer, and a region made of the first conductive layer, the second conductive layer, and a third conductive layer;
• wherein the semiconductor layer includes a channel forming region, a first impurity region of one conductivity type, and a second impurity region of the one conductivity type sandwiched between the channel forming region and the first impurity region of the one conductivity type and being in contact with the channel forming region, and
• wherein a part of the second impurity region of the one conductivity type overlaps with the gate electrode.

A semiconductor device in which a pixel region having at least one n-channel thin film transistor comprising:

• a gate electrode of the n-channel thin film transistor including a first conductive layer being in contact with a gate insulating film;
• a gate wiring line connected to the gate electrode of the n-channel thin film transistor and including a region made of the first conductive layer and a second conductive layer, and a region made of the first conductive layer, the second conductive layer, and a third conductive layer;
• and
• a semiconductor layer of the n-channel thin film transistor including a channel forming region, a first impurity region of one conductivity type, and a second impurity region of the one conductivity type sandwiched between the channel forming region and the first impurity region of the one conductivity type and being in contact with the channel forming region,
• wherein a part of the second impurity region of the one conductivity type overlaps with the gate electrode.

A semiconductor device having a CMOS circuit comprising an n-channel thin film transistor and a p-channel thin film transistor, comprising:

• a gate electrode of the n-channel thin film transistor including a first conductive layer being in contact with a gate insulating film;
• a gate wiring line connected to the gate electrode of the n-channel thin film transistor including a region made of the first conductive layer and a second conductive layer, and a region made of the first conductive layer, the second conductive layer, and a third conductive layer;
• and
• a semiconductor layer of the n-channel thin film transistor including a channel forming region, a first impurity region of one conductivity type, and a second impurity region of the one conductivity type sandwiched between the channel forming region and the first impurity region of the one conductivity type and being in contact with the channel forming region,
• wherein a part of the second impurity region of the one conductivity type overlaps with the gate electrode.

A semiconductor device having a pixel region having an n-channel thin film transistor and a CMOS circuit having an n-channel thin film transistor and a p-channel thin film transistor, comprising:

• a gate electrode of each of the n-channel thin film transistors in the pixel region and the CMOS circuit including a first conductive layer being in contact with a gate insulating film;
• a gate wiring line connected to the gate electrode of each of the n-channel thin film transistors in the pixel region and the CMOS circuit and including a region made of the first conductive layer and a second conductive layer, and a region made of the first conductive layer, the second conductive layer, and a third conductive layer;
• and
• a semiconductor layer of each of the n-channel thin film transistors in the pixel region and the CMOS circuit including a channel forming region, a first impurity region of one conductivity type, and a second impurity region of the one conductivity type sandwiched between the channel forming region and the first impurity region of the one conductivity type and being in contact with the channel forming region,
• wherein a part of the second impurity region of the one conductivity type overlaps with the gate electrode.

A semiconductor device in which two n-channel thin film transistors in one pixel, comprising:

• a gate electrode of each of the two n-channel thin film transistors including a first conductive layer being in contact with a gate insulating film;
• a gate wiring line connected to the gate electrode of each of the n-channel thin film transistors including a region made of the first conductive layer and a second conductive layer, and a region made of the first conductive layer, the second conductive layer, and a third conductive layer;
• a semiconductor layer of one of the two n-channel thin film transistors including a channel forming region, a first impurity region of one conductivity type, and a second impurity region of the one conductivity type sandwiched between the channel forming region and the first impurity region of the one conductivity type and being in contact with the channel forming region, a part of the second impurity region including a region overlapping with the gate electrode and a region not overlapping with the gate electrode;
• and
• a semiconductor layer of the other of the two n-channel thin film transistors including a channel forming region, a first impurity region of the one conductivity type, and a second impurity region of the one conductivity type sandwiched between the channel forming region and the first impurity region of the one conductivity type and being in contact with the channel forming region, a part of the second impurity region includes a region overlapping with the gate electrode.

A semiconductor device having an n-channel thin film transistor and a p-channel thin film transistor in one pixel, comprising:

• a gate electrode of each of the n-channel thin film transistor and the p-channel TFT including a first conductive layer and being in contact with a gate insulating film;
• a gate wiring line connected to the gate electrodes of the n-channel thin film transistor and the p-channel TFT including a region comprising the first conductive layer and a second conductive layer, and a region comprising the first conductive layer, the second conductive layer, and a third conductive layer;
• a semiconductor layer of the n-channel thin film transistor including a channel forming region, a first impurity region of one conductivity type, and a second impurity region of the one conductivity type sandwiched between the channel forming region and the first impurity region of the one conductivity type and being in contact with the channel forming region, a part of the second impurity region including a region overlapping with the gate electrode and a region not overlapping with the gate electrode;
• and
• a semiconductor layer of the p-channel thin film transistor including a channel forming region and a third impurity region of a conductivity type opposite to the one conductivity type.