# US 6,468,891 B2 · Stereolithographically fabricated conductive elements, semiconductor device components and assemblies including such conductive elements, and methods

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- Number: US 6,468,891 B2
- Document ID: US6468891B2
- Status: Granted
- Kind: B2
- Application number: 09/843,118
- Filed: 2001-04-26
- Published: 2001-11-01
- Granted: 2002-10-22
- Earliest claimed: 2000-02-24
- Assignees: Micron Technology, Inc.
- Inventors: Vernon M. Williams
- Web page: https://patentgrep.com/patent/US6468891B2

## CPC

- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- B33Y 10/00: Processes of additive manufacturing
- B33Y 70/00: Materials specially adapted for additive manufacturing
- B33Y 80/00: Products made by additive manufacturing
- H05K 3/0023: {by exposure and development of a photosensitive insulating layer}
- H05K 3/02: in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K 3/32: electrically connecting electric components or wires to printed circuits
- H05K 3/321: by conductive adhesives
- H05K 3/4664: {Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders (H05K3/4647 takes precedence)}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/465: {Bumps or wires}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 90/00: Package configurations
- B33Y 30/00: Apparatus for additive manufacturing; Details thereof or accessories therefor
- H05K 2203/0514: Photodevelopable thick film, e.g. conductive or insulating paste
- H05K 2203/107: Using laser light
- H05K 2203/1469: Circuit made after mounting or encapsulation of the components
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/655: Fan-out layouts
- H10W 72/07131: {Means for applying material, e.g. for deposition or forming coatings}
- H10W 72/075: {of bond wires}
- H10W 72/251: {Materials}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/951: {Materials of bond pads}
- H10W 90/10: Configurations of laterally-adjacent chips
- Y02P 80/30: Reducing waste in manufacturing processes; Calculations of released waste quantities
- Y10T 29/49117: Conductor or circuit manufacturing
- Y10T 29/49126: Assembling bases
- Y10T 29/49128: Assembling formed circuit to base
- Y10T 29/4913: Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T 29/49155: Manufacturing circuit on or in base
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B33Y: ADDITIVE MANUFACTURING, i.e. MANUFACTURING OF THREE-DIMENSIONAL [3D] OBJECTS BY ADDITIVE DEPOSITION, ADDITIVE AGGLOMERATION OR ADDITIVE LAYERING, e.g. BY 3D PRINTING, STEREOLITHOGRAPHY OR SELECTIVE LASER SINTERING
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

Stereolithographically fabricated conductive elements and semiconductor device components and assemblies including these conductive elements. The conductive elements may include multiple superimposed, contiguous, mutually adhered layers of a conductive material, such as a thermoplastic conductive elastomer or a metal. In semiconductor device assemblies, the stereolithographically fabricated conductive elements may electrically connect semiconductor device components to one another. The conductive elements may alternatively comprise conductive traces or vias of circuit boards or interposers. A stereolithographic method for fabricating the conductive elements may include use of a machine vision system with at least one camera operably associated with a computer controlling a stereolithographic application of material so that the system may recognize the position, orientation, and features of a semiconductor device assembly, semiconductor die, or other substrate on which the conductive element is to be fabricated.

## Claims

### Claim 1

A method for fabricating at least one conductive element for use with at least one semiconductor device component, comprising:
providing the at least one semiconductor device component;
defining a first layer of the at least one conductive element from substantially unconsolidated conductive material at least partially over said at least one semiconductor device component;
defining at least one additional layer of the at least one conductive structure from substantially unconsolidated conductive material at least partially superimposed over said first layer; and
permitting said substantially unconsolidated conductive material to at least partially consolidate.

### Claim 2 (depends on 1)

The method of claim 1, wherein said providing comprises providing said at least one semiconductor device component comprises providing a substrate layer of a carrier substrate.

### Claim 3 (depends on 2)

The method of claim 2, wherein said defining said first layer comprises defining said first layer to be substantially entirely carried by said substrate layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein said providing comprises providing at least two semiconductor device components.

### Claim 5 (depends on 4)

The method of claim 4, wherein said defining said first layer comprises defining said first layer to electrically connect said at least two semiconductor device components.

### Claim 6 (depends on 4)

The method of claim 4, wherein said providing said at least two semiconductor device components comprises providing a semiconductor die.

### Claim 7 (depends on 4)

The method of claim 4, wherein said providing said at least two semiconductor device components comprises providing a lead frame.

### Claim 8 (depends on 4)

The method of claim 4, wherein said providing said at least two semiconductor device components comprises providing a packaged semiconductor device.

### Claim 9 (depends on 1)

The method of claim 1, wherein said defining said first layer and said defining said at least one additional layer comprise defining said first layer and said at least one additional layer from an at least partially liquified thermoplastic conductive elastomer.

### Claim 10 (depends on 1)

The method of claim 1, wherein said defining said first layer and said defining said at least one additional layer comprise defining said first layer and said at least one additional layer from an at least partially uncured conductive photopolymer.

### Claim 11 (depends on 1)

The method of claim 1, wherein said defining said first layer and said defining said at least one additional layer comprise defining said first layer and said at least one additional layer from metal.

### Claim 12 (depends on 1)

The method of claim 1, wherein said permitting said substantially unconsolidated conductive material to at least partially consolidate comprises permitting said substantially unconsolidated conductive material to at least partially harden.

### Claim 13 (depends on 1)

The method of claim 1, wherein said permitting said substantially unconsolidated conductive material to at least partially consolidate comprises selectively consolidating said substantially unconsolidated conductive material in selected regions of each of said first layer and said at least one additional layer.

### Claim 14 (depends on 13)

The method of claim 13, wherein said permitting said substantially unconsolidated conductive material to at least partially consolidate comprises directing a laser beam onto said selected regions.