Semiconductor memory having double data rate transfer technique
AssigneeKabushiki Kaisha Toshiba
InventorsKatsuyuki Fujita, Kaoru Nakagawa
Life of this patent
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Abstract
The semiconductor memory includes a memory cell which handles a clock signal, an address fetch and a command circuit. The memory cell is designated by an address signal and stores data. The clock signal is supplied thereto so as to provide timing for an access to the memory cell, and the clock signal has a leading edge and a trailing edge. The address fetch circuit fetches the address signal for designating the memory cell in synchronism with both of the leading edge and trailing edge of the clock signal. The command circuit fetches a command signal for instructing the access to the memory cell in synchronism with both of the leading edge and the trailing edge of the clock signal.
Claims17
A semiconductor memory comprising:
- a memory cell for storing data, said memory cell being designated by an address signal;
- an address fetch circuit for fetching said address signal for designating said memory cell in synchronism with both of a leading edge and a trailing edge of a clock signal, said clock signal for providing timing for access to said memory cell;
- and
- a command circuit for fetching a command signal for instructing said access to said memory cell in synchronism with both of said leading edge and said trailing edge of said clock signal.
A semiconductor memory comprising:
- a memory cell for storing data, said memory cell being designated by an address signal;
- a clock generating circuit for generating a clock signal used for providing timing for an access to said memory cell, said clock signal having a leading edge and a trailing edge;
- a first holding circuit for holding said address signal for designating said memory cell in synchronism with either one of a leading edge and a trailing edge of said clock signal;
- a second holding circuit for holding said address signal in synchronism with an other edge which comes after said one of edges, which is different from said one of said edges, used by said first holding circuit to hold said address signal;
- a first decoding circuit for decoding said address signal held by said first holding circuit;
- and
- a second decoding circuit for decoding said address signal held by said second holding circuit.
A semiconductor memory comprising:
- a memory cell for storing data;
- a clock generating circuit for generating a clock signal used for providing timing for an access to said memory cell, said clock signal having a leading edge and a trailing edge;
- a first holding circuit for holding a command signal for instructing said access to said memory cell in synchronism with either one of said leading edge and said trailing edge of said clock signal;
- a second holding circuit for holding said command signal in synchronism with an other edge which comes after said one of edges, which is different from said one of said edges, used by said first holding circuit to hold said command;
- a first decoding circuit for decoding said command signal held by said first holding circuit;
- and
- a second decoding circuit for decoding said command signal held by said second holding circuit.
Dependencies are inferred from the claim text.