DRAM sense amplifier having pre-charged transistor body nodes

A sense amplifier comprising:

• an amplifier circuit formed in a substrate, said amplifier circuit comprising:
• a first transistor having a body node of a first conductivity in said substrate;
• a second transistor having a body node of said first conductivity in said substrate;
• and
• active region in said substrate, said active region contacting said body nodes of said first and second transistors.

A sense amplifier comprising:

• an amplifier circuit formed in a substrate, said amplifier circuit comprising:
• a first transistor having a body node of a first conductivity in said substrate;
• a second transistor having a body node of said first conductivity in said substrate;
• an active region in said substrate, said active region contacting said body nodes of said first and second transistors;
• and
• a first diode connected between said body node of said first transistor and one of a source region and a drain region of said first transistor.

A memory device comprising:

• a plurality of memory cells arranged in rows and columns;
• a plurality of pairs of digit lines, each of said plurality of pairs of digit lines being associated with at least one of said plurality of memory cells;
• and
• a plurality of sense amplifiers, each of said plurality of sense amplifiers comprising:
• a first amplifier circuit connected between one of said plurality of pairs of digit lines, said first amplifier circuit having a first transistor and a second transistor, each of said first transistor and said second transistor having a body node;
• a third transistor having a first terminal connected to said body node of said first and second transistor, a second terminal connected to a voltage potential, and a gate terminal connected to receive a first control signal,
• wherein before said first amplifier circuit is activated, said first control signal turns on said third transistor to connect said voltage potential to said body node of said first and second transistor to thereby charge said body node of said first and second transistor to said voltage potential, and when said first amplifier circuit is activated said first control signal turns off said third transistor to disconnect said voltage potential from said body node of said first and second transistor.

A memory device formed on a substrate, said memory device comprising:

• a plurality of memory cells arranged in rows and columns;
• a plurality of pairs of digit lines, each of said plurality of pairs of digit lines being associated with at least one of said plurality of memory cells;
• and
• a plurality of sense amplifiers, each of said plurality of sense amplifiers comprising:
• an amplifier circuit formed in said substrate, said amplifier circuit comprising:
• a first transistor having a body node of a first conductivity in said substrate;
• a second transistor having a body node of said first conductivity in said substrate;
• and
• an active region in said substrate, said active region contacting said body nodes of said first and second transistors.

A memory device formed on a substrate, said memory device comprising:

• a plurality of memory cells arranged in rows and columns;
• a plurality of pairs of digit lines, each of said plurality of pairs of digit lines being associated with at least one of said plurality of memory cells;
• and
• a plurality of sense amplifiers, each of said plurality of sense amplifiers comprising:
• an amplifier circuit formed in said substrate, said amplifier circuit comprising:
• a first transistor having a body node of a first conductivity in said substrate;
• a second transistor having a body node of said first conductivity in said substrate;
• an active region in said substrate, said active region contacting said body nodes of said first and second transistors;
• and
• a first diode connected between said body node of said first transistor and one of a source region and a drain region of said first transistor.

A processor system comprising:

• a central processing unit;
• and
• a memory device connected to said processing unit to receive data from and supply data to said central processing unit, said memory device comprising:
• a plurality of memory cells arranged in rows and columns;
• a plurality of pairs of digit lines, each of said plurality of pairs of digit lines being associated with at least one of said plurality of memory cells;
• and
• a plurality of sense amplifiers, each of said plurality of sense amplifiers comprising:
• a first amplifier circuit connected between one of said plurality of pairs of digit lines, said first amplifier circuit having a first transistor and a second transistor, each of said first transistor and said second transistor having a body node;
• a third transistor having a first terminal connected to said body node of said first and second transistor, a second terminal connected to a voltage potential, and a gate terminal connected to receive a first control signal,
• wherein before said first amplifier circuit is activated, said first control signal turns on said third transistor to connect said voltage potential to said body node of said first and second transistor to thereby charge said body node of said first and second transistor to said voltage potential, and when said first amplifier circuit is activated said first control signal turns off said third transistor to disconnect said voltage potential from said body node of said first and second transistor.

A method for operating a sense amplifier, said sense amplifier including an amplifier circuit having a plurality of transistors, each of said plurality of transistors having a body node, said method comprising the steps of:

• connecting said body node of at least one of said plurality of transistors of said amplifier circuit to a voltage potential;
• charging said body node of said at least one of said plurality of transistors to said voltage potential;
• disconnecting said body node of said at least one of said plurality of transistors of said amplifier circuit from said voltage potential;
• and
• providing an operation signal to said amplifier circuit to activate said amplifier circuit.

A method for operating a sense amplifier, said sense amplifier including a first and second amplifier circuit, each of said first and second amplifier circuits having a plurality of transistors, each of said plurality of transistors having a body node, said method comprising the steps of:

• connecting said body node of at least one of said plurality of transistors of said first and second amplifier circuit to a voltage potential;
• charging said body node of said at least one of said plurality of transistors of said first and second amplifier circuit to said voltage potential;
• disconnecting said body node of said at least one of said plurality of transistors of said first and second amplifier circuit from said voltage potential;
• and
• providing an operation signal to said amplifier circuit to activate said amplifier circuit.