Circuitry and method for resetting memory without a write cycle

A memory system, comprising:

• a Content Addressable Memory (CAM) block including a plurality of locations operable to store a plurality of contents thereat;
• an age_array operably associated with said CAM block for monitoring said plurality of locations to determine whether a particular location of said CAM block is available for storing new content data thereat, said age_array comprising a plurality of age_cells, each corresponding to a specific location in said CAM block;
• set means provided with each age_cell to store a binary 1 in said age_cell when a select location of said CAM block corresponding to said age_cell includes contents that match an externally supplied search data;
• and
• reset means provided with each age_cell to clear said age_cell during a read operation with respect to said age_cell, said means operating in response to at least a reset control, signal generated to indicate that said read operation is substantially complete.

A method of resetting a memory storage cell without a write cycle, comprising the steps of:

• upon application of a clock signal to initiate a read cycle with respect to said memory storage cell, activating a wordline associated with said memory storage cell;
• developing a voltage separation between data and data bar nodes associated with said memory storage cell, said voltage separation being indicative of a binary data value stored thereat;
• sensing said binary data value on bit and bit bar lines coupled to said data and data bar nodes, respectively, and thereby generating a data out signal;
• generating a reset control signal indicating that said sensing step is substantially complete;
• and
• applying said reset control signal to said memory storage cell's data node in order to store a binary 0 thereat without a separate write cycle.