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US 6,466,071 B2Granted
Methods and circuits for correcting a duty-cycle of a signal
AssigneeSamsung Electronics Co., Ltd.
InventorsKyu-hyoun Kim, Jung-bae Lee
Life of this patent
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Abstract
A signal is duty-cycle corrected by delaying the signal to generate a delayed version of the signal and generating an output signal that transitions from a first state to a second state responsive to a transition of the signal from the first state to the second state and a transition of the delayed version of the signal from the second state to the first state. The output signal transitions from the second state to the first state responsive to a transition of the signal from the second state to the first state and a transition of the delayed version of the signal from the first state to the second state.
Claims30
A method of correcting a duty-cycle of a signal, comprising:
- delaying the signal for a predetermined time to generate a delayed version of the signal, wherein the predetermined time is selected from the group consisting of a time in which the signal is in a first state during a single cycle of the signal and a time in which the signal is in a second state during the single cycle of the signal;
- and
- generating an output signal that transitions from the first state to the second state responsive to a transition of the signal from the first state to the second state and a transition of the delayed version of the signal from the second state to the first state, and that transitions from the second state to the first state responsive to a transition of the signal from the second state to the first state and a transition of the delayed version of the signal from the first state to the second state.
A method of correcting a duty-cycle of a signal, comprising:
- limiting a slew rate of the signal to generate a first intermediate output signal;
- determining a voltage difference between the first intermediate output signal and a reference voltage;
- generating an output signal responsive to the voltage difference between first intermediate output signal and the reference voltage;
- delaying the output signal to generate a delayed version of the output signal;
- and
- generating the reference voltage responsive to the output signal and the delayed version of the output signal.
3 more elements
A duty-cycle correction circuit, comprising:
- a delay circuit that is configured to generate a delayed signal for a predetermined period of time responsive to an input signal, wherein the predetermined time is selected from the group consisting of a time in which the signal is in a first state during a single cycle of the signal and a time in which the signal is in a second state during the single cycle of the signal;
- and
- a mixer circuit that is configured to generate an output signal that transitions from the first state to the second state responsive to a transition of the input signal from the first state to the second state and a transition of the delayed signal from the second state to the first state, and that transitions from the second state to the first state responsive to a transition of the input signal from the second state to the first state and a transition of the delayed signal from the first state to the second state.
A duty-cycle correction circuit, comprising:
- a differential amplifier circuit that is configured to generate an output signal responsive to an input signal and a reference voltage;
- a delay circuit that is configured to generate a delayed signal responsive to the output signal;
- and
- a control circuit that is configured to generate the reference voltage responsive to the output signal and the delayed signal.
1 more element
A duty-cycle correction circuit, comprising:
- means for delaying a signal for a predetermined time to generate a delayed version of the signal, wherein the predetermined time is selected from the group consisting of a time in which the signal is in a first state during a single cycle of the signal and a time in which the signal is in a second state during the single cycle of the signal;
- and
- means for generating an output signal that transitions from the first state to the second state responsive to a transition of the signal from the first state to the second state and a transition of the delayed version of the signal from the second state to the first state, and that transitions from the second state to the first state responsive to a transition of the signal from the second state to the first state and a transition of the delayed version of the signal from the first state to the second state.
A duty-cycle correction circuit, comprising:
- means for limiting a slew rate of a signal to generate a first intermediate output signal;
- means for determining a voltage difference between the first intermediate output signal and a reference voltage;
- means for generating an output signal responsive to the voltage difference between first intermediate output signal and the reference voltage;
- means for delaying the output signal to generate a delayed version of the output signal;
- and
- means for generating the reference voltage responsive to the output signal and the delayed version of the output signal.
3 more elements
Dependencies are inferred from the claim text.