MOS structure with improved substrate-triggered effect for on-chip ESD protection

A PMOS device structure with a high substrate-triggered effect, the PMOS device structure formed on an N-type well in a substrate, the PMOS device structure comprising:

• a gate in the N-type well;
• a first P+ diffusion region in the N-type well for use as a drain of the PMOS device structure;
• a second P+ diffusion region in the N-type well for use as a source of the PMOS device structure, the first P+ diffusion region, the N-type well and the second P+ diffusion region forming a collector, a base and an emitter of a parasitic lateral p-n-p bipolar junction transistor (BJT);
• a first N+ diffusion region in the N-type well for electrically connecting to an N-well biased circuit;
• a dummy gate between the first P+ diffusion region and the first N+ diffusion region;
• a second N+ diffusion region in the N-type well for electrically connecting to a VDD power terminal;
• and
• a shallow trench isolation (STI) structure to isolate the second P+ diffusion region and the second N+ diffusion region;
• wherein when the N-well biased circuit induces a substrate trigger current (Itrig), the substrate trigger current (Itrig) flows through the N-type well underneath the dummy gate to the first N region, causing the parasitic lateral p-n-p BJT to be turned on and quickly conduct a specific current electrically connected to the drain to the VDD power terminal through the source.

An electrostatic discharge (ESD) protection device disposed on a P-type well of a substrate, the ESD protection device comprising:

• at least one NMOS in the P-type well, a drain of the NMOS, the P-type well and a source of the NMOS forming a parasitic lateral n-p-n bipolar junction transistor (BJT), the drain of the NMOS and the source of the NMOS electrically connected to an I/O buffering pad and a VSS power terminal respectively;
• at least one first P+ diffusion region in the P-type well for electrically connecting to a P-well biased circuit;
• at least one dummy gate between the NMOS and the first P+ diffusion region;
• at least one second P+ diffusion region in the P-type well for electrically connecting to a VSS power terminal;
• and
• at least one shallow trench isolation (STI) structure to isolate the NMOS and the second P+ diffusion region;
• wherein when an ESD voltage pulse is applied to the I/O buffering pad, the P-well biased circuit induces a substrate trigger current (Itrig), the substrate trigger current (Itrig) flows into the P-type well underneath the dummy gate through the first P+ diffusion region and reaches a base of the parasitic lateral n-p-n BJT, causing the parasitic lateral n-p-n BJT to be triggered on and quickly discharge a current incurred from the ESD voltage pulse to the VSS power terminal.

An electrostatic discharge (ESD) protection device, the ESD protection device disposed on an N-type well in a substrate, the ESD protection device comprising:

• at least one PMOS in the N-type well, a drain of the PMOS, the N-type well and a source of the PMOS forming a parasitic lateral p-n-p bipolar junction transistor (BJT), the drain of the PMOS and the source of the PMOS electrically connected to an I/O buffering pad and a VDD power terminal respectively;
• at least one first N+ diffusion region in the N-type well for electrically connecting to an N-well biased circuit;
• at least one dummy gate between the PMOS and the first N+ diffusion region;
• at least one second N+ diffusion region in the N-type well for electrically connecting to the VDD power terminal;
• and
• at least one shallow trench isolation (STI) structure to isolate the PMOS and the second N+ diffusion region;
• wherein when an ESD voltage pulse is applied to the I/O buffering pad, the N-well biased circuit induces a substrate trigger current (Itrig), the substrate trigger current (Itrig) flows from the base of the parasitic lateral p-n-p BJT through the N-type well underneath the dummy gate to the first N+ diffusion region, causing the parasitic lateral p-n-p BJT to be triggered on and to quickly discharge a current incurred from the ESD voltage pulse to the VDD power terminal.

An electrostatic discharge (ESD) protection circuit electrically connected to an I/O buffering pad, an internal circuit, a VSS power terminal and a VDD power terminal, the ESD protection circuit comprising:

• a first ESD protection device electrically connected to the VSS power terminal, the I/O buffering pad and the internal circuit, the first ESD protection device comprising:
• a P-type well;
• at least one first NMOS in the P-type well, a drain of the first NMOS, the P-type well and a source of the first NMOS forming a parasitic lateral n-p-n bipolar junction transistor (BJT), the drain of the first NMOS and the source of the NMOS electrically connected to the I/O buffering pad and the VSS power terminal respectively;
• at least one first P+ diffusion region in the P-type well;
• at least one dummy gate between the first NMOS and the first P+ diffusion region;
• at least one second P+ diffusion region in the P-type well for electrically connecting to the VSS power terminal;
• and
• at least one first shallow trench isolation (STI) structure for isolating the first NMOS and the second P+ diffusion region;
• a positive substrate-biased circuit electrically connected to the VSS power terminal, the I/O buffering pad, the internal circuit and the first P+ diffusion region in the first ESD protection device, the positive substrate-biased circuit comprising:
• a second NMOS, a source of the second NMOS electrically connected to the VSS power terminal via a P-type well resistor (R_PW), a drain of the second NMOS electrically connected to the I/O buffering pad, a gate of the second NMOS electrically connected to the VSS power terminal and the I/O buffering pad via a first electrical device and a second electrical device respectively;
• a second ESD protection device structure electrically connected to the VDD power terminal, the I/O buffering pad and the internal circuit, the second ESD protection device structure comprising:
• an N-type well;
• at least one first PMOS in the N-type well, a drain of the first PMOS, the N-type well and a source of the first PMOS forming a parasitic lateral p-n-p bipolar junction transistor (BJT), the drain of the first PMOS and the source of the first PMOS electrically connected to the I/O buffering pad and the VDD power terminal respectively;
• at least one first N+ diffusion region in the N-type well;
• at least one dummy gate between the first PMOS and the first N+ diffusion region;
• at least one second N+ diffusion region in the N-type well for electrically connecting to the VDD power terminal;
• and
• at least one first shallow trench isolation (STI) structure for isolating the first PMOS and the second N+ diffusion region;
• a negative substrate-biased circuit electrically connected to the VDD power terminal, the I/O buffering pad, the internal circuit and the first N+ diffusion region in the second ESD protection device, the negative substrate-biased circuit comprising:
• a second PMOS, a source of the second PMOS electrically connected to the VDD power terminal via an N-type well resistor (R_NW), a drain of the second PMOS electrically connected to the I/O buffering pad, a gate of the second PMOS electrically connected to the VDD power terminal and the I/O buffering pad via a third electrical device and a fourth electrical device respectively.

An electrostatic discharge (ESD) protection circuit electrically connected to an I/O buffering pad, an internal circuit, a VSS power terminal, and a VDD power terminal, the ESD protection circuit comprising:

• a first ESD protection device electrically connected to the VSS power terminal, the I/O buffering pad and the internal circuit, the first ESD protection device structure comprising:
• a P-type well;
• at least one NMOS in the P-type well, a drain of the NMOS, the P-type well, and a source of the NMOS forming a parasitic lateral n-p-n bipolar junction transistor (BJT), the drain of the NMOS and the source of the NMOS electrically connected to the I/O buffering pad and the VSS power terminal, respectively;
• at least one first P+ diffusion region in the P-type well;
• at least one dummy gate between the NMOS and the first P+ diffusion region;
• at least one second P+ diffusion region in the P-type well for electrically connecting to the VSS power terminal;
• and
• at least one first shallow trench isolation (STI) structure for isolating the NMOS and the second P+ diffusion region;
• a positive substrate-biased circuit electrically connected to the VSS power terminal, the I/O buffering pad, the internal circuit, and the first P+ diffusion region in the first ESD protection device, the positive substrate-biased circuit comprising:
• a first electrical device electrically connected to the I/O buffering pad, the internal circuit, and the first P+ diffusion region in the first ESD protection device structure;
• a second electrical device electrically connected to the VSS power terminal and the first P+ diffusion region in the first ESD protection device structure;
• a second ESD protection device structure electrically connected to the VDD power terminal, the I/O buffering pad, and the internal circuit, the second ESD protection device structure comprising:
• an N-type well;
• at least one PMOS in the N-type well, a drain of the PMOS, the N-type well and a source of the PMOS forming a parasitic lateral p-n-p bipolar junction transistor (BJT), the drain of the PMOS and the source of the PMOS electrically connected to the I/O buffering pad and the VDD power terminal, respectively;
• at least one first N+ diffusion region in the N-type well;
• at least one dummy gate between the PMOS and the first N+ diffusion region;
• at least one second N+ diffusion region in the N-type well for electrically connecting to the VDD power terminal;
• and
• at least one second shallow trench isolation (STI) structure for isolating the PMOS and the second N+ diffusion region;
• a negative substrate-biased circuit electrically connected to the VDD power terminal, the I/O buffering pad, the internal circuit, and the first N+ diffusion region in the second ESD protection device, the negative substrate-biased circuit comprising:
• a third electrical device electrically connected to the I/O buffering pad, the internal circuit, and the first N+ diffusion region in the second ESD protection device structure;
• and
• a fourth electrical device electrically connected the VDD power terminal and the first N+ diffusion region in the second ESD protection device structure.

A power-rail electrostatic discharge (ESD) clamp circuit electrically connected to a VSS power terminal and a VDD power terminal, the power-rail ESD clamp circuit comprising:

• an ESD protection device, the ESD protection device comprising:
• a P-type well;
• an NMOS in the P-type well, a drain of the NMOS, the P type well, and a source of the NMOS forming a parasitic lateral n-p-n bipolar junction transistor (BJT), the drain of the first NMOS and the source of the NMOS electrically connected to the VDD power terminal and the VSS power terminal, respectively;
• at first P+ diffusion region in the P-type well;
• a dummy gate between the first NMOS and the first P+ diffusion region;
• a second P+ diffusion region in the P-type well for electrically connecting to the VSS power terminal;
• and
• a first shallow trench isolation (STI) structure for isolating the first NMOS and the second P+ diffusion region;
• a substrate-biased circuit electrically connected to the VSS power terminal, the VDD power terminal, and the first P+ diffusion region in the ESD protection device, the substrate-biased circuit comprising:
• a MOS, a source of the MOS electrically connected to the VSS power terminal via a P-type well resistor (R_PW), a drain of the MOS electrically connected to the VDD power terminal, a gate of the MOS electrically connected to the VSS power terminal and the VDD power terminal via a first electrical device and a second electrical device, respectively.

A power-rail electrostatic discharge (ESD) clamp circuit electrically connected to a VSS power terminal and a VDD power terminal, the power-rail ESD clamp circuit comprising:

• an ESD protection device, the ESD protection device comprising:
• a P-type well;
• an NMOS in the P-type well, a drain of the NMOS, the P-type well, and a source of the NMOS forming a parasitic lateral n-p-n bipolar junction transistor (BJT), the drain of the NMOS and the source of the NMOS electrically connected to the VDD power terminal and the VSS power terminal, respectively;
• a first P+ diffusion region in the P-type well;
• a dummy gate between the NMOS and the first P+ diffusion region;
• a second P+ diffusion region in the P-type well for electrically connecting to the VSS power terminal;
• and
• a first shallow trench isolation (STI) structure for isolating the NMOS and the second P+ diffusion region;
• a substrate-biased circuit electrically connected to the VSS power terminal, the VDD power terminal, and the first P+ diffusion region in the ESD protection device structure, the substrate-biased circuit comprising:
• a resistor electrically connected to the VSS power terminal and the first P+ diffusion region in the ESD protection device;
• and
• a zener diode electrically connected to the VDD power terminal, the resistor, and the first P+ diffusion region of the first ESD protection device.