Semiconductor processing methods and structures for determining alignment during semiconductor wafer processing

A semiconductor processing method of determining alignment during semiconductor wafer processing comprising:

• forming a first layer over a substrate;
• forming a first pattern within the first layer, said first pattern defining only a single, four-sided geometric figure;
• forming a second layer over the first layer;
• forming an alignment pattern over the second layer, said alignment pattern overlapping with the first pattern to define an alignment pattern portion which, when viewed from a point over the substrate, is disposed outwardly of the four sides of the first pattern;
• and
• inspecting said first and alignment patterns and ascertaining from said alignment pattern portion whether a misalignment exists between the patterns, and if so, a magnitude of misalignment, wherein one of said first and alignment patterns defines a rectangle and another of said first and alignment patterns defines a parallelogram having non-right angles.

A semiconductor processing method of determining alignment during semiconductor wafer processing comprising:

• forming a first layer over a substrate;
• forming a first pattern within the first layer, said first pattern defining only a single, four-sided geometric figure;
• forming a second layer over the first layer;
• forming an alignment pattern over the second layer, said alignment pattern overlapping with the first pattern to define an alignment pattern portion which when viewed from a point over the substrate, is disposed outwardly of the four sides of the first pattern;
• and
• inspecting said first and alignment patterns and ascertaining from said alignment pattern portion whether a misalignment exists between the patterns, and if so, a magnitude of misalignment, wherein said first pattern defines a rectangle and said alignment pattern defines a parallelogram.

A semiconductor processing method of determining alignment during semiconductor wafer processing comprising:

• forming a first layer over a substrate;
• forming a first pattern within the first layer, said first pattern defining only a single, four-sided geometric figure;
• forming a second layer over the first layer;
• forming an alignment pattern over the second layer, said alignment pattern overlapping with the first pattern to define an alignment pattern portion which, when viewed from a point over the substrate, is disposed outwardly of the four sides of the first pattern;
• and
• inspecting said first and alignment patterns and ascertaining from said alignment pattern portion whether a misalignment exists between the patterns, and if so, a magnitude of misalignment, wherein:
• said first pattern defines a rectangle and said alignment pattern defines a parallelogram;
• and
• said alignment pattern portion defines a triangle.

A method of determining alignment during semiconductor wafer processing comprising:

• forming a first pattern, the first pattern being a single, enclosed, multi-sided, generally rectilinearly-formed pattern within a layer provided over a substrate by etching a plurality of joined edges into the layer, each edge being joined with two other edges to define the first pattern;
• forming a masking layer over said layer;
• superimposing, in said masking layer, a second pattern comprising a multi-sided, generally rectilinearly-formed pattern, over the first pattern, at least one side of the second pattern, when viewed from a point over the substrate, being disposed at an angle which is generally oblique relative to one side of the first pattern;
• and
• inspecting relative positions between the first and second patterns to determine alignment in one direction.

A method of determining alignment during semiconductor wafer processing comprising:

• forming a first pattern over a semiconductor substrate, said first pattern comprising only four sides which are joined with one another;
• superimposing a second pattern over the first pattern, said second pattern being defined by a plurality of sides arranged at predetermined angles relative to one another which are different from predetermined angles at which first pattern sides are arranged;
• providing a series of graduations proximate one of the first and second patterns;
• inspecting relative positions between the first and second patterns to ascertain alignment between the two patterns;
• and
• inspecting the series of graduations to quantify the misalignment when inspecting ascertains misalignment.

A semiconductor wafer alignment method comprising:

• defining a first pair of lines within a layer over a substrate;
• and
• defining a second pair of lines over the first pair of lines and arranged to define a visually-detectable, shift-recognizable relationship in which a shift of one of the pairs of lines in one direction is translated into a quantifiable magnitude in another direction, said magnitude being ascertainable through visual inspection of the first and second pairs of lines and the use of the geometric principles of similar triangles, and further comprising:
• defining a third pair of lines within said layer over said substrate;
• and
• defining a fourth pair of lines over the third pair of lines and arranged to define a visually-detectable, second shift-recognizable relationship in which a shift of one of the third and fourth pairs of lines in a direction which is different from said one direction is translated into a second quantifiable magnitude in another different direction, said second magnitude being ascertainable through visual inspection of the third and fourth pairs of lines.