Apparatus and method for testing master logic units within a data processing apparatus

A data processing apparatus, comprising:

• one or more master logic units for accessing a bus in order to generate processing requests;
• a test controller for testing said master logic units of the data processing apparatus;
• an arbiter for receiving bus request signals from the test controller and the one or more master logic units, and for applying predetermined priority criteria to control access to the bus by the test controller and the master logic units, the predetermined priority criteria identifying the relative priority of each master logic unit and the test controller;
• in a normal test mode, the test controller having a higher priority than any of the master logic units to be tested;
• and
• in a master test mode, when master functionality of a first master logic unit is to be tested by the test controller, the arbiter being arranged to receive a priority access signal to cause the arbiter to assign the first master logic unit a higher priority than the test controller, in order to allow the first master logic unit to have access to the bus in order to generate a test processing request, wherein the priority access signal comprises a priority enable signal arranged to cause the arbiter to assign the first master logic unit a higher priority than the test controller, such that the first master logic unit will be given access to the bus upon issuing its normal bus request signal, wherein the master logic unit is arranged to assert its normal bus request signal to request access to the bus in order to enable the test processing request to be driven onto the bus, and the arbiter is arranged to grant the first master logic unit access to the system bus if the priority enable signal is asserted.

A data processing apparatus comprising:

• one or more master logic units for accessing a bus in order to generate processing requests;
• a test controller for testing said master logic units of the data processing apparatus;
• an arbiter for receiving bus request signals from the test controller and the one or more master logic units, and for applying predetermined priority criteria to control access to the bus by the test controller and the master logic units, the predetermined priority criteria identifying the relative priority of each master logic unit and the test controller;
• in a normal test mode, the test controller having a higher priority than any of the master logic units to be tested;
• and
• in a master test mode, when master functionality of a first master logic unit is to be tested by the test controller, the arbiter being arranged to receive a priority access signal to cause the arbiter to assign the first master logic unit a higher priority than the test controller, in order to allow the first master logic unit to have access to the bus in order to generate a test processing request, wherein the first master logic unit contains a test register from which the priority access signal is asserted, and the priority access signal is asserted to the arbiter by the first master logic unit when the first master logic unit is to be tested in said master test mode.

A data processing apparatus comprising:

• one or more master logic units for accessing a bus in order to generate processing requests;
• a test controller for testing said master logic units of the data processing apparatus;
• an arbiter for receiving bus request signals from the test controller and the one or more master logic units, and for applying predetermined priority criteria to control access to the bus by the test controller and the master logic units, the predetermined priority criteria identifying the relative priority of each master logic unit and the test controller;
• in a normal test mode, the test controller having a higher priority than any of the master logic units to be tested;
• and
• in a master test mode, when master functionality of a first master logic unit is to be tested by the test controller, the arbiter being arranged to receive a priority access signal to cause the arbiter to assign the first master logic unit a higher priority than the test controller, in order to allow the first master logic unit to have access to the bus in order to generate a test processing request, wherein:
• the arbiter comprises a priority encoder for receiving the priority access signal and any bus request signals from the test controller and the one or more master logic units;
• the arbiter being arranged to apply the predetermined priority criteria in the absence of said priority access signal in order to generate a signal identifying which of the test controller and master logic units requesting the bus has the highest priority;
• and
• the arbiter being arranged upon receipt of the priority access signal to assign the first master logic unit a higher priority than the test controller irrespective of the predetermined priority criteria and to generate a signal identifying the highest priority master logic unit requesting the bus.

A method of testing a master logic unit within a data processing apparatus, the data processing apparatus comprising one or more master logic units arranged to access a bus in order to generate processing requests, a test controller for testing logic units of the data processing apparatus, and an arbiter for receiving bus request signals from the test controller and the one or more master logic units, and for applying predetermined priority criteria to control access to the bus by the test controller and the master logic units, the predetermined priority criteria identifying the relative priority of each master logic unit and the test controller, the method comprising the steps of:

• (a) arranging the test controller to initiate a test of master functionality of the first master logic unit in a master test mode;
• (b) issuing a priority access signal to bit to cause the arbiter to assign the first master logic unit a higher priority than the test controller;
• (c) granting the first master logic unit access to the system bus;
• and
• (d) arranging the first master logic unit to generate a test processing request.

A method of testing a master logic unit within a data processing apparatus, the data processing apparatus comprising one or more master logic units arranged to access a bus in order to generate processing requests, a test controller for testing logic units of the data processing apparatus, and an arbiter for receiving bus request signals from the test controller and the one or more master logic units, and for applying predetermined priority criteria to control access to the bus by the test controller and the master logic units, the predetermined priority criteria identifying the relative priority of each master logic unit and the test controller, the method comprising the steps of:

• (a) arranging the test controller to initiate a test of master functionality of the first master logic unit in a master test mode;
• (b) issuing a priority access signal to the arbiter to cause the arbiter to assign the first master logic unit a higher priority than the test controller;
• (c) granting the first master logic unit access to the system bus;
• and
• (d) arranging the first master logic unit to generate a test processing request,
• wherein said step (b) comprises the step of the first master logic unit asserting the priority access signal to the arbiter when the first master logic unit is to be tested in said master test mode.