Programmable and electrically configurable latch timing circuit

In an integrated circuit including a first latch circuit for sensing and latching, at a particular time when enabled by a latch enable signal, a differential signal that increases in magnitude over a period of time, a latch timing circuit comprising:

• a first configurable delay circuit having an input terminal for receiving an input timing signal, having an output terminal for conveying an output timing signal for controlling the timing of the latch enable signal, said first configurable delay circuit responsive to a plurality of timing settings, various individual timing settings of said plurality providing for different delays through the first configurable delay circuit such that the latch enable signal is selectable to occur, after receiving the input timing signal, at one of a plurality of various times corresponding to various magnitudes of the differential signal;
• and
• a first timing setting control circuit for generating and communicating a selected one of the plurality of timing settings to the first configurable delay circuit;
• wherein the first timing setting control circuit is programmable to configure one of the plurality of timing settings as the programmed timing setting, and to normally communicate the programmed timing setting as the selected timing setting;
• and
• wherein the first timing setting control circuit is electrically configurable, at least when not already programmed, to temporarily communicate as the selected timing setting one of the plurality of timing settings.

A method of manufacturing an integrated circuit including a latch circuit for sensing and latching, at a particular time when enabled by a latch enable signal, a differential signal that increases in magnitude over a period of time, said method comprising:

• providing within the integrated circuit a latch timing circuit for controlling the timing of the latch enable signal, said latch timing circuit including a configurable delay circuit responsive to an input timing signal and a plurality of timing settings, various individual timing settings of which provide for different delays through the configurable delay circuit such that the latch enable signal is selectable to occur, after receiving the input timing signal, at one of a plurality of various times corresponding to various magnitudes of the differential signal;
• testing the integrated circuit to determine which of the timing settings is the most aggressive timing setting for which the integrated circuit functions without error;
• and
• programming the configurable delay circuit to a particular timing setting relative to the most aggressive timing setting for which the integrated circuit functions without error, as determined during testing.

In an integrated circuit including a first latch circuit for sensing and latching, at a particular time when enabled by a latch enable signal, a differential signal that increases in magnitude over a period of time, a latch timing circuit comprising:

• a first configurable delay circuit having an input terminal for receiving an input timing signal, having an output terminal for conveying an output timing signal for controlling the timing of the latch enable signal, and having at least one control input for communicating a selected one of a plurality of timing settings to the first configurable delay circuit, various individual timing settings of which provide for different delays through the first configurable delay circuit such that the latch enable signal is selectable to occur, after receiving the input timing signal, at one of a plurality of various times corresponding to various magnitudes of the differential signal;
• and
• a first timing setting control circuit for generating and communicating the selected one of the plurality of timing settings to the first configurable delay circuit;
• wherein the first timing setting control circuit is arranged to initially communicate a default timing setting as the selected timing setting, said default timing setting being a predetermined one of the plurality of timing settings;
• wherein the first timing setting control circuit is programmable to configure a timing setting other than the default timing setting as the programmed timing setting and to normally communicate the programmed timing setting as the selected timing setting;
• and
• wherein the first timing setting control circuit is electrically configurable to temporarily communicate as the selected timing setting, if not already programmed, a timing setting other than the default timing setting or, if already programmed, a timing setting other than the programmed timing setting.