Lossless switching DC-to-DC converter

A lossless switching DC-to-DC converter for providing power from a DC voltage source connected between an input terminal and a common input terminal to a DC load connected between an output terminal and a common output terminal, said converter comprising:

• (1) an input inductor connected at one end thereof to said input terminal;
• (2) an output inductor connected at one end thereof to said output terminal;
• (3) a middle inductor connected at one end thereof to said common input terminal and said common output terminal;
• (4) a resonant inductor connected at one end thereof to a second end of said middle inductor;
• (5) an input capacitor, having one end connected to a second end of said input inductor and second end of said input capacitor connected to a second end of said resonant inductor;
• (6) an input switch with one end connected to said common input terminal and a second end of said input switch connected to said second end of said input inductor;
• (7) an output switch with one end connected to said common output terminal and a second end of said output switch connected to said second end of said output inductor;
• (8) a complementary output switch, having one end connected to said second end of said output inductor and a second end of said complementary output switch connected to said second end of said middle inductor;
• (9) a branch comprising a complementary input switch and an auxiliary capacitor connected in series;
• (10) switching time control means for providing a precise pattern of turning ON and turning OFF signals for said input switch, said complementary input switch, said output switch and said complementary output switch, with a referenced time interval DTS during which said input switch is turned ON and a complementary time interval D′TS=(1−D)TS during which said input switch is turned OFF, where D is a variable and controllable duty ratio and D′ is a complementary duty ratio within one complete switch operating cycle TS;
• (11) means for connecting the ends of said branch to said converter whereby during said complementary time intervals D′TS current through said branch is equal to the sum of current flowing into said one end of said input inductor and current flowing into said one end of said middle inductor reduced by current flowing out of said one end of said output inductor;
• wherein no current flows through said branch during said referenced time interval DTS, and only AC current flows through said branch during said complementary time interval D′TS;
• wherein said input switch, said complementary input switch, and said complementary output switch are semiconductor current bidirectional switching devices, capable of conducting the current in both directions while in an ON-state, and sustaining voltage in one direction, while in an OFF-state, and said semiconductor current bidirectional switching devices are modeled as the parallel connection of an ideal switch, a parasitic body-diode and a parasitic capacitance;
• wherein said output switch is a semiconductor voltage bidirectional switching device, capable of conducting the current while in an ON-state, and sustaining voltage in both directions, while in an OFF-state, and said semiconductor voltage bidirectional switching device is a composite switch whose model consists of the parallel connection of an ideal switch, and an equivalent parasitic capacitance;
• wherein a DC-to-DC voltage conversion ratio of said converter depends linearly on said operating duty ratio D;
• wherein said switching time control means includes precise electronically controlling operation of said semiconductor current bi-directional and voltage bi-directional switching devices whereby two transitions, first transition D to D′ and second transition D′ to D, are obtained during each successive switch operating cycle TS wherein said transition intervals are short compared to said switch operating cycle, and said switching time control means provides control signals for respective switches as follows:
• said first transition D to D′ is initiated by turning said input switch OFF and, when voltage on said complementary output switch is reduced to zero, said switching time control means provides control signal for complementary output switch to be turned ON at zero voltage for zero switching losses, and said first transition continues until the voltage on said complementary input switch reduces to zero, at which instant said switching time control means provides control signal for said complementary input switch to be also turned ON at zero voltage for zero switching losses, and said first transition continues further until the current through the output switch is reduced to zero, making this the latest instant at which output switch must be turned OFF to complete said first transition D to D′;
• said second transition D′ to D is initiated by turning said complementary input switch OFF to start linear discharge of said parasitic capacitor across said input switch, and, when voltage across said input switch drops to zero said input switch is turned ON by said switching time control means at zero voltage and with zero switching losses, and said output switch is by said switching time control means simultaneously turned ON with a voltage across said output switch equal to negative value of said DC voltage source, and said second transition continues with a current-reversal subinterval during which the input capacitor current is reversed from being equal to input inductor current to current flow in opposite direction with magnitude equal to middle inductor current at which instant the current through the complementary output switch is reduced to zero making this the latest instant at which complementary output switch must be turned OFF to complete said second transition D′ to D;
• wherein said resonant capacitance is significantly higher than capacitance of parasitic capacitors across said output switch and said complementary output switch, and
• whereby during said second transition D′ to D said input switch is turned ON at zero voltage, hence substantially reducing switching losses and voltage stress on said semiconductor devices and increasing efficiency of said converter with reduced electromagnetic interference;
• whereby a lossless switching cycle is provided based on the precise pattern of the switch timing of said semiconductor current bidirectional and voltage bi-directional switching devices by said switching time control means;
• whereby the switching at zero voltage of the complementary input switch during D to D′ transition and input switch during D′ to D transition is achieved for any operating point, that is, for all input DC source voltage and for any DC load current from no load to full load.

An isolated lossless switching DC-to-DC converter for providing power from a DC voltage source connected between an input terminal and a common input terminal to a DC load connected between an output terminal and a common output terminal, said converter comprising:

• (1) an input inductor connected at one end thereof to said input terminal;
• (2) an output inductor connected at one end thereof to said output terminal;
• (3) an isolation transformer with primary winding and secondary winding placed on a common magnetic core, and each winding having one dot-marked end and another unmarked end whereby any AC voltage applied to said primary winding of said isolation transformer induces AC voltage in said secondary winding of said isolation transformer so that two AC voltages are in phase at dot-marked ends of said primary and secondary windings of said isolation transformer, wherein said primary winding of said isolation transformer is connected at a dot-marked end thereof to said common input terminal and said secondary winding of said isolation transformer is connected at a dot-marked end thereof to said common output terminal;
• (4) an input capacitor, having one end connected to an unmarked end of said primary winding of said isolation transformer and second end of said input capacitor connected to a second end of said input inductor;
• (5) an input switch with one end connected to said common input terminal and a second end of said input switch connected to said second end of said input inductor;
• (6) an output switch with one end connected to said common output terminal and a second end of said output switch connected to said second end of said output inductor;
• (7) a complementary output switch, having one end connected to said second end of said output inductor and a second end of said complementary output switch connected to an unmarked end of said secondary winding of said isolation transformer;
• (8) a branch comprising a complementary input switch and an auxiliary capacitor connected in series, wherein one end of said branch is connected to dot-marked end of said primary winding of said isolation transformer and another end of said branch is connected to said unmarked end of said input inductor;
• (9) switching time control means for providing a precise pattern of turning ON and turning OFF signals for said input switch, said complementary input switch, said output switch and said complementary output switch, with a referenced time interval DTS during which said input switch is turned ON and a complementary time interval D′TS=(1−D)TS during which said input switch is turned OFF, where D is a variable and controllable duty ratio and D′ is a complementary duty ratio within one complete switch operating cycle TS;
• wherein no current flows through said branch during said referenced time interval DTS, and only AC current flows through said branch during said complementary time interval D′TS;
• wherein said input switch, said complementary input switch, said output switch, and said complementary output switch are semiconductor current bidirectional switching devices, capable of conducting the current in both directions while in an ON-state, and sustaining voltage in one direction, while in an OFF-state, and said semiconductor current bidirectional switching devices are each modeled as a parallel connection of an ideal switch, a parasitic body-diode and a parasitic capacitance;
• wherein said primary winding and said secondary winding are tightly coupled for reduced leakage between said primary winding and said secondary winding;
• wherein said isolation transformer with leakage inductance is modeled as a perfectly coupled transformer with no leakage with an effective leakage inductance connected in series with its primary winding;
• wherein a DC-to-DC voltage conversion ratio of said isolated lossless switching converter depends linearly on said operating duty ratio D;
• wherein turns ratio of said secondary winding to said primary winding of said isolation transformer provides additional scaling of DC-to-DC voltage conversion ratio of said isolated lossless switching converter;
• wherein said switching time control means includes precise electronically controlling operation of said semiconductor current bidirectional switching devices whereby two transitions, first transition D to D′ and second transition D′ to D, are obtained during each successive switch operating cycle TS wherein said transition intervals are short compared to said switch operating cycle, and said switching time control means provides control signals for respective switches as follows:
• said first transition D to D′ is initiated by turning said input switch OFF and, when voltage on said complementary output switch is reduced to zero, said switching time control means provides control signal for complementary output switch to be turned ON at zero voltage for zero switching losses, and said first transition continues until the voltage on said complementary input switch reduces to zero, at which instant said switching time control means provides control signal for said complementary input switch to be also turned ON at zero voltage for zero switching losses, and said first transition continues until the current through the output switch is reduced to zero, making this the latest instant at which output switch must be turned OFF to complete said first transition D to D′, and
• said second transition D′ to D is initiated by first turning said output switch ON, intentionally before said complementary input switch is turned OFF, to boost the current in said leakage inductance by an additional magnitude which is inversely proportional to said leakage inductance, directly proportional to voltage difference between DC voltage of said auxiliary capacitor and DC voltage of said DC voltage source and directly proportional to this boost subinterval during which said output switch and said complementary input switch are both turned ON, and when said complementary input switch is turned OFF, the resonant discharge of parasitic capacitor across said input switch and simultaneous resonant charge of parasitic capacitor across said complementary input switch take place during this resonant subinterval in which the total resonant current is comprising three distinct current components, the first one a cosinusoidal resonant current component with said additional magnitude defined above, the second one a sinusoidal resonant current component whose magnitude is directly proportional to voltage difference between DC voltage of said auxiliary capacitor and DC voltage of said DC voltage source and inversely proportional to a characteristic impedance of resonant circuit which is equal to a square root of the ratio of said leakage inductance and capacitance of resonant capacitance equal to the sum of parasitic capacitors of said input switch and said complementary input switch, and the third one a cosinusoidal resonant current component whose magnitude is equal to initial current value in said leakage inductance at the instant when said output switch was turned ON, and at the instant when said parasitic capacitor of said input switch is fully discharged, said switching time control means provides a control signal for said input switch to be turned ON at zero voltage and with zero switching losses to complete said resonant subinterval, and said second transition continues with a current-reversal subinterval during which the input capacitor current is reversed from being equal to input inductor current to current flow in opposite direction with magnitude equal to a magnetizing current of said isolation transformer (same as a primary current of said isolation transformer during said referenced time interval DTS) at which instant the current through the complementary output switch is reduced to zero making this the latest instant at which complementary output switch must be turned OFF to complete said second transition D′ to D,
• wherein said resonant capacitance is significantly higher than capacitance of parasitic capacitors across said output switch and said complementary output switch, and
• whereby said isolation transformer provides a galvanic isolation between said input DC voltage source and said DC load, and
• whereby a lossless switching cycle is provided based on the precise pattern of the switch timing of said semiconductor current bidirectional switching devices by said switching time control means;
• during this lossless switching cycle, electrical charge is transferred between parasitic capacitors in a lossless manner, and during said second transition D′ to D said complementary input switch and said output switch are kept simultaneously ON as long as needed for sufficient additional energy storage in said leakage inductance of said isolation transformer to increase the peak resonant current of said leakage inductance of said isolation transformer, just enough to enable complete discharge of said parasitic capacitor of said input switch to zero volts and complete said second transition D′ to D with substantially reduced switching losses and voltage stress on said semiconductor switching devices and increased efficiency of said converter with reduced electromagnetic interference, and said lossless switching is especially effective for DC-to-DC conversion when said duty ratio D is well below 0.5 and said DC voltage source is very high as in rectified utility AC line voltage.

An isolated lossless switching DC-to-DC converter for providing power from a DC voltage source connected between an input terminal and a common input terminal to a DC load connected between an output terminal and a common output terminal, said converter comprising:

• (1) an input inductor connected at one end thereof to said input terminal;
• (2) an output inductor connected at one end thereof to said output terminal;
• (3) an isolation transformer with primary winding and secondary winding placed on a common magnetic core, and each winding having one dot-marked end and another unmarked end whereby any AC voltage applied to said primary winding of said isolation transformer induces AC voltage in said secondary winding of said isolation transformer so that two AC voltages are in phase at dot-marked ends of said primary and secondary windings of said isolation transformer, wherein said primary winding of said isolation transformer is connected at a dot-marked end thereof to said common input terminal and said secondary winding of said isolation transformer is connected at a dot-marked end thereof to said common output terminal;
• (4) an input capacitor, having one end connected to an unmarked end of said primary winding of said isolation transformer and second end of said input capacitor connected to a second end of said input inductor;
• (5) an input switch with one end connected to said common input terminal and a second end of said input switch connected to said second end of said input inductor;
• (6) an output switch with one end connected to said common output terminal and a second end of said output switch connected to said second end of said output inductor;
• (7) a complementary output switch, having one end connected to said second end of said output inductor and a second end of said complementary output switch connected to an unmarked end of said secondary winding of said isolation transformer;
• (8) a branch comprising a complementary input switch and an auxiliary capacitor connected in series, wherein one end of said branch is connected to dot-marked end of said primary winding of said isolation transformer and another end of said branch is connected to said unmarked end of said input inductor;
• (9) switching time control means for providing a precise pattern of turning ON and turning OFF signals for said input switch, said complementary input switch, said output switch and said complementary output switch, with a referenced time interval DTS during which said input switch is turned ON and a complementary time interval D′TS=(1−D)TS during which said input switch is turned OFF, where D is a variable and controllable duty ratio and D′ is a complementary duty ratio within one complete switch operating cycle TS;
• wherein no current flows through said branch during said referenced time interval DTS, and only AC current flows through said branch during said complementary time interval D′TS;
• wherein said input switch, said complementary input switch, and said complementary output switch are semiconductor current bidirectional switching devices, capable of conducting the current in both directions while in an ON-state, and sustaining voltage in one direction, while in an OFF-state, and said semiconductor current bidirectional switching devices are modeled as comprising the parallel connection of an ideal switch, a parasitic body-diode and a parasitic capacitance;
• wherein said output switch is a semiconductor voltage bidirectional switching device, capable of conducting the current while in an ON-state, and sustaining voltage in both directions, while in an OFF-state, and said semiconductor voltage bidirectional switching device is a composite switch whose model consists of the parallel connection of an ideal switch, and an equivalent parasitic capacitance;
• wherein said primary winding and said secondary winding are tightly coupled for reduced leakage between said primary winding and said secondary winding;
• wherein said isolation transformer with leakage inductance is modeled as a perfectly coupled transformer with no leakage with an effective leakage inductance connected in series with its primary winding;
• wherein a DC-to-DC voltage conversion ratio of said isolated lossless switching converter depends linearly on said operating duty ratio D;
• wherein turns ratio of said secondary winding to said primary winding of said isolation transformer provides additional scaling of DC-to-DC voltage conversion ratio of said isolated lossless switching converter;
• wherein said switching time control means includes precise electronically controlling operation of said semiconductor current bidirectional and voltage bi-directional switching devices whereby two transitions, first transition D to D′ and second transition D′ to D, are obtained during each successive switch operating cycle TS wherein said transition intervals are short compared to said switch operating cycle, and said switching time control means provides control signals for respective switches as follows:
• said first transition D to D′ is initiated by turning said input switch OFF and, when voltage on said complementary output switch is reduced to zero, said switching time control means provides control signal for complementary output switch to be turned ON at zero voltage for zero switching losses, and said first transition continues until the voltage on said complementary input switch reduces to zero, at which instant said switching time control means provides control signal for said complementary input switch to be also turned ON at zero voltage for zero switching losses, and said first transition continues further until the current through the output switch is reduced to zero, making this the latest instant at which output switch must be turned OFF to complete said first transition D to D′;
• said second transition D′ to D is initiated by turning said complementary input switch OFF to start linear discharge of said parasitic capacitor across said input switch, and, when voltage across said input switch drops to zero said input switch is turned ON by said switching time control means at zero voltage and with zero switching losses, and said output switch is by said switching time control means simultaneously turned ON with a voltage across said output switch equal to negative value of said DC voltage source, and said second transition continues with a current-reversal subinterval during which the input capacitor current is reversed from being equal to input inductor current to current flow in opposite direction with magnitude equal to middle inductor current at which instant the current through the complementary output switch is reduced to zero making this the latest instant at which complementary output switch must be turned OFF to complete said second transition D′ to D;
• wherein said resonant capacitance is significantly higher than capacitance of parasitic capacitors across said output switch and said complementary output switch, and whereby during said second transition D′ to D said input switch is turned ON at zero voltage, hence substantially reducing switching losses and voltage stress on said semiconductor devices and increasing efficiency of said converter with reduced electromagnetic interference;
• whereby a lossless switching cycle is provided based on the precise pattern of the switch timing of said semiconductor current bidirectional and voltage bi-directional switching devices by said switching time control means;
• whereby the switching at zero voltage of the complementary input switch during D to D′ transition and input switch during D′ to D transition is achieved for any operating point, that is, for all input DC source voltage and for any DC load current from no load to full load.