Enhanced embedded logic analyzer

A method for reprogramming a programmable logic device (PLD) in a system, said method comprising:

• receiving an electronic design intended for said PLD;
• specifying internal signals of said electronic design to monitor;
• specifying a first breakpoint;
• compiling said electronic design with said internal signals, said first breakpoint and a logic analyzer to produce a first design file;
• programming said PLD with said first design file, said logic analyzer being embedded in said PLD and arranged to store said internal signals before occurrence of said first breakpoint;
• specifying a second breakpoint;
• recompiling said electronic design with said internal signals, said second breakpoint and said logic analyzer to produce a second design file;
• and
• reprogramming said PLD with said second design file, said logic analyzer being embedded in said PLD and arranged to store said internal signals before occurrence of said second breakpoint, whereby said PLD is reprogrammed while in said system.

A method for receiving sample data from a logic analyzer embedded within a programmable logic device (PLD), said method comprising:

• establishing communication with a logic analyzer embedded within a programmable logic device (PLD);
• specifying a breakpoint indicative of the state of at least one signal within said PLD;
• indicating to said logic analyzer to continuously store internal signals of said PLD in a memory of said logic analyzer such that said internal signals are stored before the occurrence of said breakpoint;
• and
• receiving said stored internal signals from said logic analyzer, said stored signals representing at least signals stored before said breakpoint, whereby said stored internal signals may be viewed on a user computer.

A programmable logic device (PLD) comprising:

• PLD circuitry representing one iteration of an electronic design in a design process to create a final PLD;
• logic analyzer circuitry integrated within said PLD circuitry such that a portion of said PLD circuitry is connected to said logic analyzer circuitry;
• a state machine within said logic analyzer circuitry for initiating the capture of signals from said PLD circuitry before a breakpoint occurs;
• and
• sample memory circuitry within said logic analyzer circuitry arranged to capture said signals before said breakpoint occurs, whereby said sample memory circuitry is available to present said captured signals for analysis after said capture.