Method and apparatus for a late pipeline enhanced floating point unit

A method of providing a pipeline of functional units that use a latchless clocking method for logic synchronization with a late pipe N-NARY functional unit that executes instructions without stalling until the result is available, comprising:

• providing one or more earlier N-NARY functional units;
• and
• coupling a late pipe N-NARY functional unit coupled to said earlier N-NARY functional unit, said late pipe N-NARY functional unit does not begin executing instructions until all of the input operands are or will be available for execution so that said late pipe N-NARY functional unit will execute instructions without stalling until the result will be available in a fixed number of cycles wherein said earlier N-NARY functional units and said late pipe N-NARY functional unit use a latchless clocking method for logic synchronization.

A method of pipelining instructions and operands with a pipeline of N-NARY functional units that use a latchless clocking method for logic synchronization with a late pipe N-NARY functional unit that executes instructions without stalling until the result is available, comprising:

• pipelining the instruction through one or more earlier N-NARY functional units;
• and
• executing the instruction in a late pipe N-NARY functional unit coupled to said earlier N-NARY functional unit, said late pipe N-NARY functional unit does not begin executing instructions until all of the input operands are or will be available for execution so that said late pipe N-NARY functional unit will execute instructions without stalling until the result will be available in a fixed number of cycles wherein said earlier N-NARY functional units and said late pipe N-NARY functional unit use a latchless clocking method for logic synchronization.

A system of pipelining instructions and operands with a pipeline of functional units that use a latchless clocking method for logic synchronization with a late pipe N-NARY functional unit that executes instructions without stalling until the result is available, comprising:

• one or more earlier N-NARY functional units;
• and
• a late pipe N-NARY functional unit coupled to said earlier N-NARY functional unit, said late pipe N-NARY functional unit does not begin executing instructions until all of the input operands are or will be available for execution so that said late pipe N-NARY functional unit will execute instructions without stalling until the result will be available in a fixed number of cycles wherein said earlier N-NARY functional units and said late pipe N-NARY functional unit use a latchless clocking method for logic synchronization.

A dependent claim according to claim 1, 7, 13, or 4 wherein said late pipe N-NARY functional unit is non-cancelable.