Apparatus and method for signal processing

Associative signal processing apparatus comprising:

• an array of processors, each processor including a multiplicity of associative memory cells, at least one of said processors being operative to process a plurality of samples of an incoming signal;
• a register array including at least one register operative to store responders arriving from the processors and to provide communication between processors;
• and
• an I/O buffer register operative to input an incoming signal and to output an outgoing signal;
• wherein the order in which the I/O buffer inputs an image differs from the row/column order of the image and wherein the register array is operative to perform at least one multicell shift operation.

Associative signal processing apparatus comprising:

• an array of processors, each processor including a multiplicity of associative memory cells, at least one of said processors being operative to process a plurality of samples of an incoming signal;
• a register array including at least one register operative to store responders arriving from the processors and to provide communication between processors;
• and
• an I/O buffer register operative to input an incoming signal and to output an outgoing signal;
• wherein the order in which the I/O buffer inputs the samples differs from the order of the samples within the incoming signal and wherein the register array is operative to perform at least one multicell shift operation.

Associative signal processing apparatus comprising:

• an array of processors, each processor including a multiplicity of associative memory cells, at least one of the processors being operative to process a plurality of samples of an incoming signal;
• a register array including at least one register operative to store responders arriving from the processors and to provide communication between processors;
• an I/O buffer register operative to input all incoming signal and to output an outgoing signal;
• and
• an image correction system whereby:
• (i) a multiplicity of pixels from a distorted image are provided to a respective multiplicity of said associative memory cells;
• (ii) a transformation for an output of said image to compensate for said distortion is provided;
• and
• (iii) said transformation is executed in parallel for a plurality of said pixels via said register array.

Associative signal processing apparatus for processing, an incoming signal comprising a plurality of samples, the apparatus comprising:

• two-dimensional array of processors each processor including a multiplicity of content addressable memory cells, each sample of an incoming signal being processed by at least one of the processors;
• a register array including at least one register operative to store responders arriving from the processors and to provide communication, within a single cycle, between non-adjacent processors;
• and
• image correction system whereby:
• (i) a multiplicity of pixels from a distorted image are provided to a respective multiplicity of said content addressable memory cells;
• (ii) a transformation for an output of said image to compensate for said distortion is provided;
• and
• (iii) said transformation is executed in parallel for a plurality of said pixels via said register array.

Associative signal processing apparatus for processing an incoming signal comprising a plurality of samples, the apparatus comprising:

• a two-dimensional array of processors, each said processor including a multiplicity of content addressable memory cells, each sample of an incoming signal being processed by at least one of said processors;
• a register array including at least one register operative to store responders arriving from the processors and to provide communication, within a single cycle, between non-adjacent processors, said at least one register providing communication between processors which are processing non-adjacent samples;
• and
• an I/O buffer register operative to input and output a signal;
• wherein the processor array, the register array and the I/O buffer register are arranged on a single silicon die and wherein the I/O buffer register includes a plurality of buffer register cells whose number is at least equal to the number of processors in said two-dimensional array.

Associative signal processing apparatus comprising:

• an array of processors, each processor including a multiplicity of associative memory cells, at least one of said processors being operative to process a plurality of samples of an incoming signal;
• a register array including at least one register operative to store responders arriving from the processors and to provide communication between processors;
• and
• an I/O buffer register operative to input an incoming signal and to output an outgoing signal;
• wherein the order in which the I/O buffer inputs an image differs from the row/column order of the image and wherein the word length of the I/O buffer register is increasable by decreasing the word length of the associative memory cells.

Associative signal processing apparatus comprising:

• an array of processors, each processor including a multiplicity of associative memory cells, at least one of said processors being operative to process a plurality of samples of an incoming signal;
• a register array including at least one register operative to store responders arriving from the processors and to provide communication between processors;
• and
• an I/O buffer register operative to input an incoming signal and to output an outgoing signal;
• wherein the order in which the I/O buffer inputs the samples differs from the order of the samples within the incoming signal and wherein the word length of the I/O buffer register is increasable by decreasing the word length of the associative memory cells.