Automatic design of VLIW instruction formats
AssigneeHewlett-Packard Company
InventorsShail Aditya Gupta, B. Ramakrishna Rau, Richard C. Johnson, Michael S. Schlansker
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Abstract
A computer-implemented method automates the design of efficient binary instruction encodings of VLIW instruction formats. The method automatically finds compact instruction formats that can express and exploit the full parallelism specified in the underlying processor microarchitecture, subject to constraints on alignment and decode hardware complexity. The method can be guided by statistics about the composition and frequency of program instructions, so that the instruction format design is customized to a particular set of applications or an application domain.
Claims20
A method for-programmatic design of a VLIW processor instruction format from an input specification including specified processor operations, instruction level parallelism constraints among the specified operations, and a datapath representation of the processor, the method comprising:
- based on the specified processor operations, the instruction level parallelism constraints, and the datapath representation, programmatically constructing a bit allocation problem specification identifying instruction fields that are to be assigned to bit positions in the instruction format of the processor, bit width requirements of the instruction fields, and instruction field conflict constraints;
- and
- programmatically allocating bit positions in the processor to the instruction fields in the bit allocation problem specification.
A method for optimizing a VLIW processor instruction format from a concrete instruction set architecture specification including an instruction format specification, register file specification, and desired concurrency relationships among operation groups;
- wherein the instruction format specification includes instructions, instruction fields within each of the instruction templates, and bit positions and encodings for the instruction fields;
- and
- wherein the register file specification includes register files having a specified number of registers, and a correspondence between operand instruction fields in the instruction format specification and a register file;
- the method comprising:
- programmatically extracting an abstract instruction set architecture specification including specified processor operations and instruction level parallelism constraints among the specified operations;
- based on the abstract instruction set architecture, the desired concurrency relationships among operation groups, and the register file specification, programmatically constructing a bit allocation problem specification identifying instruction fields that are to be assigned to bit positions in the instruction format of the processor, bit width requirements of the instruction fields, and instruction field conflict constraints;
- and
- programmatically allocating bit positions in the processor to the instruction fields in the bit allocation problem specification.
A method for programmatic design of a VLIW processor instruction format, the method comprising:
- in a computer readable data structure, providing a bit allocation problem specification including instruction fields that are to be assigned to bit positions in the instruction format of the processor, bit width requirements of the instruction fields, and instruction field conflict constraints;
- and
- programmatically allocating bit positions in the processor to the instruction fields in the bit allocation problem specification such that the instruction field conflict constraints are satisfied.
A method for programmatic design of a VLIW processor instruction format, the method comprising:
- based on output from a re-targetable compiler, extracting usage statistics indicating frequency of use of processor operations in an application program;
- and
- based on the usage statistics, programmatically generating custom instruction templates for VLIW instructions that each include a combination of selected frequently used processor operations such that each instruction template specifies a set of operations that are allowed to be issued in parallel for execution in a VLIW processor.
A method for programmatic design of a VLIW processor instruction format from an input specification including specified processor operations, instruction level parallelism constraints among the specified operations, and a datapath representation of the processor, the method comprising:
- programmatically reading the input specification of the specified processor operations, the instruction level parallelism constraints, and the datapath representation;
- and
- based on the input specification, programmatically constructing a bit allocation problem specification for VLIW processor instructions identifying instruction fields in the VLIW processor instructions that are to be assigned to bit positions in the instruction format of the processor, bit width requirements of the instruction fields, and instruction field conflict constraints.
Dependencies are inferred from the claim text.