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AssigneeUnisys Corporation
InventorsLarry L. Byers, Jerome G. Carlin, Michael R. Overley, Gary R. Robeck, Lloyd E. Thorsbakken
Estimating the term…
An improved fault detection system and method for detecting the occurrence of faults within the addressing logic of a storage device is provided. Data stored to a selected address within a storage device includes a copy of the selected address. During a subsequent read operation, the copy of the address is read from memory and compared to the read address used to perform the memory access. If the addresses are not the same, a potential addressing fault occurred within the control logic of the storage device. The fault detection system is particularly adaptable for use with storage devices having a relatively small number of addressable locations, each containing a relatively large number of bits. According to one embodiment of the invention, the storage device is a General Register Array (GRA) utilized as a queue.
A system for verifying addressing logic included in a storage device, wherein the storage device includes a plurality of addressable locations each for storing data signals, and wherein predetermined ones of the addressable locations stores, as ones of the data signals, address signals indicative of the address for the respective one of the predetermined ones of the addressable locations, the system, comprising:
The storage system, comprising:
A method for verifing addressing logic included within a storage device, comprising the steps of:
Dependencies are inferred from the claim text.