Nucleation for improved flash erase characteristics

A method of tailoring the erase speed and erase uniformity of a flash memory device, the method comprising:

• forming a tunnel dielectric layer;
• depositing nucleation sites on top of the tunnel dielectric layer by exposing the tunnel dielectric layer to a first set of deposition conditions;
• and
• depositing a polysilicon floating gate layer on top of the nucleation sites by exposing the nucleation sites to a second set of deposition conditions different from the first set of deposition conditions, the polysilicon floating gate layer having tailored polysilicon grain sizes and density.

A method of tailoring the crystal morphology of a crystalline transistor electrode in an integrated circuit, the method comprising:

• forming a dielectric layer;
• depositing nucleation sites on top of the dielectric layer by exposing the dielectric layer to a first set of deposition conditions selected to optimize grain density;
• and
• depositing a polycrystalline layer on top of the nucleation sites by exposing the nucleation sites to a second set of deposition conditions selected to optimize grain size.