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US 6,452,859 B1Granted
Dynamic semiconductor memory device superior in refresh characteristics
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsHiroki Shimano, Katsumi Dosaka, Kazutami Arimoto
Life of this patent
Estimating the term…
Abstract
A sense operation by a sense amplifier circuit is carried out by selecting a pair of subword lines simultaneously and coupling each bit line in a pair to a memory cell. Since complementary data are stored into these two memory cells, the voltage between the bit lines in a pair in a sense operation can be set large enough to allow increase of the refresh interval. Therefore, power consumption in a data retaining mode can be reduced.
Claims35
A semiconductor memory device comprising:
- a plurality of memory cells arranged in rows and columns;
- a plurality of word lines arranged corresponding to the rows, each word line having memory cells of a corresponding row connected;
- a plurality of bit lines arranged corresponding to the columns, each bit line having memory cells of a corresponding column connected, said plurality of bit lines being arranged in pairs, and each memory cell being arranged at a crossing between one of bit lines forming the pair and a corresponding word line;
- row select circuitry for simultaneously selecting word lines on an addressed row and a related row according to an address signal, said related row being selected such that a memory cell is arranged corresponding to each respective crossing between the word lines on said addressed row and said related row and the bit lines forming the pair, said row select circuitry including a drive circuit for driving the word lines on said addressed row and said related row to a selected state individually;
- and
- a plurality of sense amplifier circuits arranged corresponding to the bit line pairs, each for amplifying differentially potential of a corresponding bit line pair when rendered active.
3 more elements
A semiconductor memory device comprising:
- a plurality of memory subarrays, each memory subarray including a plurality of memory cells arranged in rows and columns;
- a plurality of subword lines arranged corresponding to the rows of memory cells in each of the memory subarrays, each subword line having memory cells on a corresponding row connected;
- a plurality of main word lines extending in a row direction common to said plurality of memory subarrays, each main word line arranged corresponding to a predetermined number of subword lines in each memory subarray;
- a plurality of subword line drivers arranged corresponding to said plurality of subword lines, each subword line driver driving a corresponding subword line to a selected state according to a signal on a corresponding main word line and a subdecode signal, said subdecode signal specifying simultaneously two subword lines in said predetermined number of subword lines, and the two subword lines specified by said subdecode signal being connected by conductive lines at both ends thereof;
- a plurality of bit line pairs arranged corresponding to the columns of memory cells in each memory subarray, each bit line pair having memory cells of a corresponding columns connected, in each bit line pair, a memory cell connected to each bit line corresponding to each respective crossing with the two subword lines specified simultaneously by the subdecode signal;
- and
- a plurality of sense amplifier circuits provided corresponding to said plurality of bit line pairs, each for amplifying differentially a voltage of a corresponding bit line pair.
4 more elements
A semiconductor memory device comprising:
- a plurality of memory cells arranged in rows and columns;
- a plurality of word lines arranged corresponding to the rows of said plurality of memory cells, each word line having memory cells on a corresponding row connected;
- a plurality of column lines arranged corresponding to the columns of said plurality of memory cells, each column line having memory cells on a corresponding column connected;
- a plurality of column voltage hold circuit provided corresponding to said plurality of column lines, for holding corresponding column lines at a predetermined voltage level in a standby state, each of said plurality of column voltage hold circuits transmitting a current-restricted voltage to a corresponding column line as said predetermined voltage.
1 more element
A semiconductor memory device comprising:
- a plurality of normal memory cells arranged in rows and columns;
- a plurality of normal subword lines arranged corresponding to the normal memory cell rows, each normal subword line having normal memory cells on a corresponding row connected;
- a plurality of normal main word lines each arranged corresponding to a predetermined number of normal subword lines;
- a plurality of spare memory cells arranged in rows of at least the predetermined number;
- a plurality of spare subword lines arranged corresponding to the spare memory cell rows, each spare subword line having spare memory rows of a corresponding row connected;
- at least one spare main word line arranged corresponding to said plurality of spare subword lines, the spare main word line being arranged corresponding to said predetermined number of the spare subword lines;
- first spare determination circuitry for determining whether a defective normal subword line is specified according to an address signal;
- second spare determination circuitry for determining whether a defective normal main word line is specified according to said address signal;
- normal row select circuitry for selectively driving a normal main word line and a normal subword line to a selected state according to said address signal and output signals of the first and second determination circuitry, said normal row select circuitry rendering said normal main word line and a corresponding normal subword line non-selected when a defect is detected by the first spare determination circuitry, and driving an addressed main word line to a selected state and selectively driving an addressed normal subword line to a selected state while maintaining predetermined normal subword lines of the predetermined number of corresponding normal subword lines to a non-selected state independent of said address signal when a defect is detected by said second spare determination circuitry;
- and
- spare row select circuitry for driving a spare main word line and a corresponding spare subword line to a selected state according to said address signal and output signals of the first and second determination circuitry, said spare row select circuitry driving the spare main word line and the corresponding spare subword line to a selected state according to said address signal when a defect is detected by said first spare determination circuitry, and driving said spare main word line to a selected state and selectively driving a spare subword line corresponding to said address signal to a selected state while maintaining a spare subword line excluding spare subword lines corresponding to said predetermined normal subword lines at a non-selected state when a defect is detected by said second determination circuitry.
8 more elements
A semiconductor memory device comprising:
- a plurality of memory cells arranged in rows and columns;
- a plurality of word lines arranged corresponding to the rows of the memory cells, each word line having memory cells of a corresponding row connected;
- and
- row select circuitry for driving a pair of word lines with one word line interposed therebetween among said plurality of word lines to a selected state simultaneously in a particular operation mode.
1 more element
Dependencies are inferred from the claim text.