Triple well no body effect negative charge pump

A negative charge pump circuit comprising:

• a first N type transistor;
• a second N type transistor wherein its drain and gate terminals are coupled to a drain terminal of said first transistor, and a source terminal of said second transistor coupled to a gate terminal of said first transistor;
• a third N type transistor wherein its source terminal is coupled to said drain terminal of said first transistor, and a drain terminal of said third transistor is coupled to said gate terminal of said first transistor;
• a fourth N type transistor wherein its drain terminal is coupled to said gate terminal of said first transistor, a source terminal of said fourth transistor coupled to a gate terminal of said third transistor, and a gate terminal of said fourth transistor coupled to said source terminal of said first transistor;
• and
• a fifth and sixth N type transistors coupled to substrate terminals of said first,:
• second, third, and fourth transistors, said fifth and sixth transistors to bias a voltage potential on said substrate terminals.

An integrated circuit device comprising:

• a triple well negative charge pump of at least two pump cells wherein each cell comprises:
• a first transistor;
• a first capacitor coupled to a source terminal of said first transistor;
• a second capacitor coupled to a gate terminal of said first transistor;
• a first diode comprising an input terminal coupled to a drain terminal of said first transistor, and an output terminal coupled to said gate terminal of said first transistor;
• a second diode comprising a control terminal coupled to a control device, an input terminal coupled to said gate terminal of said first transistor, and an output terminal coupled to said drain terminal of said first transistor;
• a first bias device to couple said source terminal of said first transistor to a substrate terminal of said first transistor, said first diode, said second diode, and said first bias device;
• and
• a second bias device to couple said drain terminal of said first transistor to said substrate terminal of said first transistor, said first diode, said second diode, and said second bias device;
• wherein a drain terminal of a first transistor of a first pump cell is coupled to a source terminal of a first transistor of a second pump cell;
• and
• a clock generator to generate clock signals to said first and second capacitors.

A method of operating a negative charge pump comprising:

• pre-charging a boot node;
• disabling a boot node discharge mechanism;
• biasing a substrate of a first N type transistor device coupled to said boot node to a first voltage potential to prevent parasitic P-N junctions from turning on in said first device;
• and
• driving a high potential on said boot node to allow charge transfer.