Efficient parallel testing of integrated circuit devices using a known good device to generate expected responses

A test system comprising:

• a reference device;
• test means for writing test data to said reference device and reading response data from said reference device;
• interface means for communicating with a plurality of semiconductor devices;
• channel means for providing at least one communication channel, said tester means, said reference device, and said interface means being communicatively interconnected to said channel means;
• and
• state machine means for controlling said interface means, said state machine means comprising a monitor state, a write state, and a read state, wherein
• while in said monitor state, said state machine means causes said interface means to monitor said channel means,
• said state machine means enters said write state upon detecting a write operation by said test means of test data to said reference device on said channel means, and while in said write state, said state machine means causes said interface means to write said test data detected on said channel means to said semiconductor device, and
• said state machine means enters said read state upon detecting a read operation by said tester of response data from said reference device, and while in said read state, said state machine causes said interface means to read said response data detected on said channel means and to read corresponding response data from said semiconductor device.