US 6,449,755 B1 · Instruction signature and primary input and primary output extraction within an IEEE 1149.1 compliance checker

Abstract

A computerized method and system for automatically extracting an IEEE 1149.1 standard design from a netlist and performing compliance checking. The present invention receives the TAP (test access port) description and compliance enable ports of a netlist. The TAP controller is extracted and its state ports are identified, referenced in a boundary scan design database (BSDD) and its states are verified. The TAP controller is controlled so that the instruction register is located and referenced in the BSDD. The TAP controller is controlled so that the bypass register is found and the BSDD is updated. The TAP controller is controlled so that the shift and update cells of the boundary scan register (BSR) are found, the control, input and output BSR cells are characterized and the BSDD is updated. Primary input and output information is also inferred and the device_ID register is found. Frontier pins are used to locate signatures of the remaining instructions and their test data registers are found. To infer the SAMPLE instruction, instructions selecting the BSR are groups and those that do not exhibit the behavior of the SAMPLE instruction are eliminated. Primary inputs and primary outputs are then inferred. The following instructions are then inferred: INTEST, HIGHZ, CLAMP, IDCODE and RUNBIST. As each of the above elements of the IEEE 1149.1 design are located, they are used to update the BSDD and are also inherently verified for compliance by the present invention. Intolerable violations flag a non-compliant design.

Claims12

Dependent claims

A computer implemented method for determining instructions that are implemented within an integrated circuit design, said method comprising the steps of:

a) extracting, from said integrated circuit design, a set of frontier pins associated with decode circuitry that is coupled to an instruction register;
b) automatically determining a set of unique signatures on said frontier pins, each unique signature representing an implemented instruction, said step b) comprising the steps of:
b1) applying opcodes to said instruction register and observing said frontier pins;
b2) recording all opcodes that map to each respective unique signature on said frontier pins and repeating step b2) for all opcodes applied at step b1);
c) extracting, from said integrated circuit design, a test data register selected by each unique signature of said set of unique signatures;
and
d) updating a design database with information obtained by steps b) and c).

4 more elements

A computer system comprising a processor coupled to a bus and a memory unit coupled to said bus, wherein instructions stored in said memory unit, when executed by said processor, implement a method for determining instructions that are implemented within a netlist, said method comprising the steps of:

a) extracting, from said netlist, a set of frontier pins associated with decode circuitry that is coupled to an instruction register;
b) automatically determining a set of unique signatures on said frontier pins, each unique signature representing an implemented instruction, said step b) comprising the steps of:
b1) applying opcodes to said instruction register and observing said frontier pins;
b2) recording all opcodes that map to each respective unique signature on said frontier pins and repeating step b2) for all opcodes applied at step b1);
c) extracting, from said netlist, a test data register selected by each unique signature of said set of unique signatures;
and
d) updating a design database with information obtained by steps b) and c).

4 more elements

Dependencies are inferred from the claim text.

Instruction signature and primary input and primary output extraction within an IEEE 1149.1 compliance checker

Life of this patent

Instruction signature and primary input and primary output extraction within an IEEE 1149.1 compliance checker

Life of this patent

Abstract

Claims12