Non-destructive method of detecting die crack problems

A method of detecting die crack problems in an integrated circuit, comprising:

• providing an integrated circuit on a die having a logic gate tree structure around the perimeter of the die, said logic gate tree structure comprising a plurality of input nodes connected with logic gates and at least one output node;
• applying under the control of a computer-implemented protocol a pattern of voltage signals at said plurality of input nodes in permutations that permit localization of any die crack problem and wherein the permutations are a minimum number of vectors necessary to determine the proper operation of each gate in the tree;
• and
• determining under the control of a computer-implemented protocol voltage signals at said at least one output node for said applied pattern of voltage signals;
• wherein the voltage signals at the at least one output node provide an indication of whether or not there is a die crack.

A system for detecting die crack problems in an integrated circuit, comprising:

• an integrated circuit on a die having a logic gate tree structure around the perimeter of the die, said integrated circuit having a plurality of input nodes and said logic gate tree structure comprising logic gates to connect at least two of the plurality of input nodes of the integrated circuit and at least one output node;
• a computer-implemented protocol capable of controlling the application of a pattern of voltage signals at said plurality of input nodes, and determining voltage signals at said at least one output node for said applied pattern of voltage signals;
• and
• a test device configured to interface said integrated circuit and said computer-implemented protocol;
• wherein the voltage signals at the at least one output node provide an indication of whether or not there is a die crack.

A system for detecting die crack problems in an integrated circuit, comprising:

• an integrated circuit on a die having a logic gate tree structure around the perimeter of the die, said logic gate tree structure comprising a plurality of input nodes and at least one output node;
• a computer-implemented protocol configured to control the application of a pattern of voltage signals at said plurality of input nodes, and to determine voltage signals at said at least one output node for said applied pattern of voltage signals;
• and
• a test device interfacing said integrated circuit and said computer-implemented protocol;
• wherein the pattern of voltages are applied to the input nodes in permutations that permit localization of any die crack problem and the permutations are a minimum number of vectors necessary to determine the proper operation of each gate in the tree;
• and
• wherein the voltage signals at the at least one output node provide an indication of whether or not there is a die crack.