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US 6,449,727 B1Granted
High-speed data transfer synchronizing system and method
AssigneeKabushiki Kaisha Toshiba
InventorHaruki Toda
Life of this patent
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Abstract
One memory controller and a plurality of memory modules are connected to a data bus line, clock bus line, and command bus line. Each memory module includes an internal clock signal generating circuit for generating internal clocks synchronizing with external clock signals output from the memory controller. This internal clock signal generating circuit has a function of adjusting the timing of a generated internal clock signal on the basis of a control signal in accordance with the position on the bus lines of a memory module having this internal clock signal generating circuit.
Claims22
A high-speed data transfer synchronizing system, comprising:
- a plurality of memory modules for receiving a clock signal to operate in synchronism with the clock signal, each of said memory modules having at least one internal clock signal generating circuit to generate at least one internal clock signal, said at least one internal clock signal synchronizing with the clock signal, said at least one internal clock signal generating circuit having a function of adjusting a generation timing of the internal clock signal having different phases from the clock signal;
- and
- a memory controller for generating and supplying the clock signal to said memory modules and transferring/receiving data to/from said memory modules.
A clock signal generating circuit comprising:
- a first buffer circuit for receiving an external clock signal;
- a first delay circuit having a signal delay time substantially equal to a signal delay time in said first buffer circuit, said first delay circuit receiving an output signal from said first buffer circuit and delaying the output signal from said first buffer circuit;
- a second delay circuit for receiving an output signal from said first delay circuit and delaying the output signal from said first delay circuit by a predetermined time;
- a second buffer circuit for receiving an output signal from said second delay circuit;
- a third delay circuit including a plurality of cascaded multi-stage first delay units to receive an output signal from said second buffer circuit and delay the output signal from said second buffer circuit, by transmitting the signal by said plurality of first delay units, for a period corresponding to a cycle of the clock signal;
- a fourth delay circuit including a plurality of cascaded multi-stage second delay units to receive a signal delayed by said third delay circuit and delay the delayed signal by transmitting the signal by the same number of second delay units as the number of first delay units by which the output signal from said second buffer circuit is transmitted;
- a variable delay circuit for receiving an output signal from said fourth delay circuit and outputting the output signal from said fourth delay circuit after delaying the signal by a time corresponding to a control signal;
- and
- a third buffer circuit having a signal delay time substantially equal to a signal delay time in said second buffer circuit, said third buffer circuit receiving an output signal from said variable delay circuit and generating an internal clock signal.
6 more elements
A high-speed data transfer synchronizing method for a high-speed data transfer synchronizing system comprising:
- a plurality of memory modules for receiving a clock signal to operate in synchronism with the clock signal, each of said memory modules having an internal clock signal generating circuit to generate at least one internal clock signal, said at least one internal clock signal synchronizing with the clock signal, said at least one internal clock signal generating circuit having a function of adjusting a generation timing of the internal clock signal on the basis of a control signal;
- and
- a memory controller for generating and supplying the clock signal to said memory modules and transferring/receiving data to/from said memory modules, comprising the steps of:
- storing a predetermined data pattern in said memory modules;
- reading out the data pattern stored in each memory module from said memory modules and transferring the readout data pattern to said memory controller;
- and
- comparing the data pattern transferred from each memory module with the original predetermined data pattern and generating the control signal such that the two data patterns match.
4 more elements
A high-speed data transfer synchronizing method for a high-speed data transfer synchronizing system comprising:
- a plurality of memory modules for receiving a clock signal to operate in synchronism with the clock signal, said memory modules previously storing a predetermined data pattern, each of said memory modules having an internal clock signal generating circuit to generate at least one internal clock signal, said at least one internal clock signal synchronizing with the clock signal, said at least one internal clock signal generating circuit having a function of adjusting a generation timing of the internal clock signal on the basis of a control signal;
- and
- a memory controller for generating and supplying the clock signal to said memory modules and transferring/receiving data to/from said memory modules, comprising the steps of:
- reading out the data pattern previously stored in each memory module and
- transferring the readout data pattern to said memory controller;
- and
- comparing the data pattern transferred from each memory module with the original data pattern previously stored in each memory module and generating the control signal such that the two data patterns match.
4 more elements
Dependencies are inferred from the claim text.