Total flexibility of predicted fetching of multiple sectors from an aligned instruction cache for instruction execution

A processor method for reducing branch instruction overhead during program execution by a processor, comprising

• executing FHT cycles for controlling the sequencing of instructions for processor execution, and providing a prediction for initiating each FHT cycle,
• initiating each FHT cycle by using a current prediction in an attempt to find a usable FHT entry, indicating a FHT hit when a FHT entry is found to match the prediction, or indicating an FHT miss when no FHT entry is found to match the prediction,
• specifying in an FHT entry having a FHT hit:
• an AIC location, a sequence of sectors in an AIC row at the specified AIC location, and an initial sector address for a first-executed sector in the specified sequence of sectors, and specifying a AIC directory address for each sector position in the AIC row, a respective AIC directory address locating a first instruction for a respective sector position in the AIC row,
• locating the sector position in the AIC row for the first-executed sector in the specified sequence of sectors, and locating a corresponding AIC directory address for the first-executed sector in the specified sequence of sectors,
• testing to determine if the corresponding AIC directory address in the specified AIC row is equal to a next instruction address indicated by the processor for the program, indicating an AIC hit if the test indicates equality, and indicating an AIC miss if the test indicates inequality,
• outputting instructions from the AIC row in the sector sequence specified by the FHT entry having a FHT hit for execution by the processor,
• generating a FHT entry during the FHT cycle having a FHT miss while using conventional instruction output sequencing controls to provide instructions for execution, and
• providing during the FHT cycle a next instruction address for a next prediction to be used by the next FHT cycle, and the next instruction address being contained in the FHT entry having an FHT hit.

Processor apparatus for reducing branch instruction overhead during program execution, comprising

• a fetch history table (FHT) for containing FHT entries that capture branch-taken and branch-not-taken histories of execution sequences of branch instructions occurring during execution of a program,
• a branch instruction prediction unit (prediction unit) connected to the FHT for indicating sequences of taken and not-taken branch outcomes for corresponding sequences of branch instructions following instruction fetch addresses in the FHT entries that indicate the beginnings of sequences of instructions represented by the FHT entries,
• an aligned instruction cache (AIC) containing rows of aligned sectors for storing sets of instructions in the program fetched from sector addresses in a computer storage hierarchy,
• an AIC directory associated with the AIC, the AIC directory containing AIC directory entries with sector positions corresponding to the rows and sectors in he AIC, the AIC directory entries containing entries having sector addresses for locating sectors of instructions in a computer storage hierarchy fetched to corresponding sectors in the AIC rows,
• FHT entry fields for recording locations of AIC rows and sector positions selected under control of the FHT entries,
• sector gates connected to the aligned sectors in the AIC rows for outputting the instructions from sectors selected by FHT entries to be sent for execution by the processor apparatus.