Circuits and methods for linearizing capacitor calibration and systems using the same

A charge redistribution analog to digital converter comprising:

• a comparator for comparing voltages presented at first and, second comparator inputs;
• an input capacitor array coupled to the first comparator input;
• an offset compensation capacitor array coupled to the first comparator input;
• a trim capacitor array coupled to the first comparator input;
• and
• switching circuitry for:
• during an offset compensation sampling phase:
• coupling a selected capacitor of the input array to a first reference voltage and a selected capacitor of the input array being calibrated to a second reference voltage;
• coupling selected capacitors of the trim array to the second reference voltage;
• and
• sampling the first and second reference voltages onto the selected capacitors of the input and trim capacitor arrays, the switching circuitry causing a voltage offset at the first input of the comparator;
• during an offset compensation conversion phase bit cycling through the capacitors of the offset compensation array to compensate for the voltage offset;
• and
• during a calibration phase, bit cycling through capacitors of the trim array to calibrate the selected capacitor of the input array being calibrated.

A switched-capacitor circuit comprising:

• a plurality of capacitor arrays coupled to a node including an input array, a trim array associated with a selected capacitor of the input array and an offset compensation array;
• a first plurality of switches for selectively coupling capacitors of the input and trim arrays to selected reference voltages to approximate an impedance presented at the node during a subsequent operation to trim the selected capacitor of the input array;
• a sampling switch for sampling the selected reference voltages onto the input and trim arrays, the sampling switch injecting a corresponding amount of charge on the node;
• and
• a second plurality of switches for selectively coupling capacitors of the offset compensation array to the selected reference voltages to compensate for the amount of charge injected on the node.