Method and apparatus for convolution encoding and viterbi decoding of data that utilize a configurable processor to configure a plurality of re-configurable processing elements

In a digital signal processing architecture comprising a core processor and a plurality of re-configurable processing elements arranged in a two-dimensional array, a method for processing digital data comprises the steps of:

• encoding a received data input by configuring one of said re-configurable processing elements to emulate a convolution encoding algorithm and applying said received data input to said convolution encoding algorithm to produce an encoded data output;
• and
• decoding a received encoded data input by configuring said plurality of re-configurable processing elements to emulate a Viterbi decoding algorithm, wherein said plurality of re-configurable processing elements is configured to accommodate every data state of said convolution encoding algorithm, and applying said received encoded data input to said Viterbi decoding algorithm to produce a decoded data output;
• wherein said encoding step further comprises initializing said one of said re-configurable processing elements by assigning register values to registers that define at least one of constraint length and code rate for said convolution encoding algorithm.

In a digital signal processing architecture comprising a core processor and a plurality of re-configurable processing elements arranged in a two-dimensional array, a method for processing digital data comprises the steps of:

• encoding a received data input by configuring one of said re-configurable processing elements to emulate a convolution encoding algorithm and applying said received data input to said convolution encoding algorithm to produce an encoded data output;
• and
• decoding a received encoded data input by configuring said plurality of re-configurable processing elements to emulate a Viterbi decoding algorithm, wherein said plurality of re-configurable processing elements is configured to accommodate every data state of said convolution encoding algorithm, and applying said received encoded data input to said Viterbi decoding algorithm to produce a decoded data output;
• wherein said encoding step further comprises generating a multiple output sequence corresponding to said received data input.

In a digital signal processing architecture comprising a core processor and a plurality of re-configurable processing elements arranged in a two-dimensional array, a method for processing digital data comprises the steps of:

• encoding a received data input by configuring one of said re-configurable processing elements to emulate a convolution encoding algorithm and applying said received data input to said convolution encoding algorithm to produce an encoded data output;
• and
• decoding a received encoded data input by configuring said plurality of re-configurable processing elements to emulate a Viterbi decoding algorithm, wherein said plurality of re-configurable processing elements is configured to accommodate every data state of said convolution encoding algorithm, and applying said received encoded data input to said Viterbi decoding algorithm to produce a decoded data output;
• wherein said encoding step further comprises performing a modulo-two addition of selected taps of a serially time-delayed sequence of said received data input.

In a digital signal processing architecture comprising a core processor and a plurality of re-configurable processing elements arranged in a two-dimensional array, a method for processing digital data comprises the steps of:

• encoding a received data input by configuring one of said re-configurable processing elements to emulate a convolution encoding algorithm and applying said received data input to said convolution encoding algorithm to produce an encoded data output;
• and
• decoding a received encoded data input by configuring said plurality of re-configurable processing elements to emulate a Viterbi decoding algorithm, wherein said plurality of re-configurable processing elements is configured to accommodate every data state of said convolution encoding algorithm, and applying said received encoded data input to said Viterbi decoding algorithm to produce a decoded data output;
• wherein said decoding step further comprises initializing said plurality of re-configurable processing elements by assigning values to registers that define at least one of constraint length and code rate for said Viterbi decoding algorithm.

In a digital signal processing architecture comprising a core processor and a plurality of re-configurable processing elements arranged in a two-dimensional array, a method for processing digital data comprises the steps of:

• encoding a received data input by configuring one of said re-configurable processing elements to emulate a convolution encoding algorithm and applying said received data input to said convolution encoding algorithm to produce an encoded data output;
• and
• decoding a received encoded data input by configuring said plurality of re-configurable processing elements to emulate a Viterbi decoding algorithm, wherein said plurality of re-configurable processing elements is configured to accommodate every data state of said convolution encoding algorithm, and applying said received encoded data input to said Viterbi decoding algorithm to produce a decoded data output;
• wherein each one of said plurality of re-configurable processing elements is configured to accommodate plural data states of said convolution encoding algorithm.

A digital signal processing architecture comprising:

• a plurality of re-configurable processing elements arranged in a two-dimensional array, said plurality of re-configurable processing elements are programmable in response to predetermined context words;
• and
• a processor operatively coupled to said plurality of re-configurable processing elements to control loading of said predetermined context words thereto, said processor being selectively operable to configure one of said re-configurable processing elements to emulate a convolution encoding algorithm, and to configure said plurality of re-configurable processing elements to emulate a Viterbi decoding algorithm wherein said plurality of re-configurable processing elements accommodates every data state of said convolution encoding algorithm;
• wherein, a received data input applied to said convolution encoding algorithm produces an encoded data output, and a received encoded data input applied to said Viterbi decoding algorithm produces a decoded data output.